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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-17 11:14:19 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-17 11:28:37 -0800 |
| commit | 1e6d56dca11c7a632b74ba51361f879dc706110a (patch) | |
| tree | 9064fcf6531f64b292821ab25e2dc3abd3f9cc2e /techlibs | |
| parent | 2bda51ac34d6f542d1d6477eecede1d6527c10b3 (diff) | |
| download | yosys-1e6d56dca11c7a632b74ba51361f879dc706110a.tar.gz yosys-1e6d56dca11c7a632b74ba51361f879dc706110a.tar.bz2 yosys-1e6d56dca11c7a632b74ba51361f879dc706110a.zip | |
+/xilinx/arith_map.v fix $lcu rule
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/arith_map.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index 5c848d4e6..c345a3da3 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -53,9 +53,9 @@ module _80_xilinx_lcu (P, G, CI, CO); ( .CYINIT(CI), .CI (1'd0), - .DI (G [(Y_WIDTH - 1):i*4]), - .S (S [(Y_WIDTH - 1):i*4]), - .CO (CO[(Y_WIDTH - 1):i*4]), + .DI (G [(WIDTH - 1):i*4]), + .S (S [(WIDTH - 1):i*4]), + .CO (CO[(WIDTH - 1):i*4]), ); // Another one end else begin @@ -63,9 +63,9 @@ module _80_xilinx_lcu (P, G, CI, CO); ( .CYINIT(1'd0), .CI (C [i*4 - 1]), - .DI (G [(Y_WIDTH - 1):i*4]), - .S (S [(Y_WIDTH - 1):i*4]), - .CO (CO[(Y_WIDTH - 1):i*4]), + .DI (G [(WIDTH - 1):i*4]), + .S (S [(WIDTH - 1):i*4]), + .CO (CO[(WIDTH - 1):i*4]), ); end |