iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Re-enable &mfs for synth_{ecp5,xilinx}	Eddie Hung	2020-01-06	2	-3/+2
*	Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactor	Eddie Hung	2020-01-06	5	-1653/+507
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\| *	Wrap arrival functions inside `YOSYS too	Eddie Hung	2020-01-06	1	-0/+2
\| *	Fix return value of arrival time functions, fix word	Eddie Hung	2020-01-06	1	-18/+14
\| *	Drive $[ABCD] explicitly	Eddie Hung	2020-01-02	1	-15/+21
\| *	Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor	Eddie Hung	2020-01-02	13	-43/+43
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\| * \|	ifndef __ICARUS__ -> ifdef YOSYS	Eddie Hung	2020-01-01	1	-2/+2
\| * \|	Rework abc9's DSP48E1 model	Eddie Hung	2020-01-01	5	-1656/+506
* \| \|	Valid to have attribute starting with SB_CARRY.	Miodrag Milanovic	2020-01-04	1	-0/+2
* \| \|	Merge pull request #1604 from whitequark/unify-ram-naming	whitequark	2020-01-02	18	-40/+67
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\| * \|	Harmonize BRAM/LUTRAM descriptions across all of Yosys.	whitequark	2020-01-01	18	-40/+67
* \| \|	Merge pull request #1601 from YosysHQ/eddie/synth_retime	Eddie Hung	2020-01-02	12	-37/+37
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\| * \| \|	Update doc that "-retime" calls abc with "-dff -D 1"	Eddie Hung	2019-12-30	11	-12/+12
\| * \| \|	Disable synth_gowin -abc9 as it offers no advantages yet	Eddie Hung	2019-12-30	1	-12/+12
\| * \| \|	Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""	Eddie Hung	2019-12-30	11	-13/+13
* \| \| \|	ifdef __ICARUS__ -> ifndef YOSYS	Eddie Hung	2020-01-01	1	-6/+6
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* \| \|	Fix anlogic async flop mapping	Eddie Hung	2020-01-01	1	-8/+8
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* \|	Update timings for Xilinx S7 cells	Eddie Hung	2019-12-30	1	-15/+35
* \|	Merge pull request #1589 from YosysHQ/iopad_default	Miodrag Milanović	2019-12-30	1	-11/+6
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\| *	Merge remote-tracking branch 'origin/master' into iopad_default	Miodrag Milanovic	2019-12-28	8	-10/+368
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\| * \|	Addressed review comments	Miodrag Milanovic	2019-12-21	1	-2/+3
\| * \|	iopad no op for compatibility with old scripts	Miodrag Milanovic	2019-12-21	1	-0/+3
\| * \|	Make iopad option default for all xilinx flows	Miodrag Milanovic	2019-12-21	1	-14/+5
* \| \|	Nitpick cleanup for ecp5	Eddie Hung	2019-12-27	2	-11/+3
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* \|	Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen	Marcin Kościelnicki	2019-12-25	3	-3/+6
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\| * \|	xilinx_dsp: Initial DSP48A/DSP48A1 support.	Marcin Kościelnicki	2019-12-22	3	-3/+6
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* /	xilinx: Test our DSP48A/DSP48A1 simulation models.	Marcin Kościelnicki	2019-12-23	5	-7/+362
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*	Add abc9_arrival times for RAM{32,64}M	Eddie Hung	2019-12-20	1	-24/+10
*	Add RAM{32,64}M to abc9_map.v	Eddie Hung	2019-12-20	1	-0/+78
*	Revert "Optimise write_xaiger"	Eddie Hung	2019-12-20	3	-15/+0
*	Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup	Eddie Hung	2019-12-19	3	-0/+15
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\| *	techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger	Eddie Hung	2019-12-06	3	-0/+15
* \|	xilinx: Add simulation models for remaining CLB primitives.	Marcin Kościelnicki	2019-12-19	3	-156/+210
* \|	xilinx_dffopt: Keep order of LUT inputs.	Marcin Kościelnicki	2019-12-19	1	-16/+30
* \|	Merge pull request #1563 from YosysHQ/dave/async-prld	David Shah	2019-12-18	2	-4/+28
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\| * \|	ecp5: Add support for mapping PRLD FFs	David Shah	2019-12-07	2	-4/+28
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* \|	xilinx: Add xilinx_dffopt pass (#1557)	Marcin Kościelnicki	2019-12-18	6	-22/+389
* \|	xilinx: Improve flip-flop handling.	Marcin Kościelnicki	2019-12-18	4	-38/+228
* \|	Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram	Eddie Hung	2019-12-16	3	-12/+301
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\| * \	Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xil...	Eddie Hung	2019-12-16	1	-2/+8
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\| \| * \|	Populate DID/DOD even if unused	Eddie Hung	2019-12-16	1	-2/+8
\| * \| \|	Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q	Eddie Hung	2019-12-16	2	-6/+6
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\| * \|	Disable RAM16X1D match rule; carry-over from LUT4 arches	Eddie Hung	2019-12-13	1	-6/+9
\| * \|	RAM64M8 to also have [5:0] for address	Eddie Hung	2019-12-13	1	-8/+8
\| * \|	Add RAM32X6SDP and RAM64X3SDP modes	Eddie Hung	2019-12-12	2	-8/+120
\| * \|	Fix RAM64M model to have 6 bit address bus	Eddie Hung	2019-12-12	1	-4/+4
\| * \|	Add memory rules for RAM16X1D, RAM32M, RAM64M	Eddie Hung	2019-12-12	2	-0/+168
* \| \|	Add unconditional match blocks for force RAM	Eddie Hung	2019-12-16	1	-4/+36
* \| \|	Update xc7/xcu bram rules	Eddie Hung	2019-12-16	1	-8/+4
* \| \|	Removing fixed attribute value to !ramstyle rules	Diego H	2019-12-15	1	-4/+4