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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 11:55:56 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 11:55:56 -0800 |
| commit | 28bf712372c494043c7adc0de904925a9199c939 (patch) | |
| tree | 89a8d64329d379fa113752361530626193f03e9c /techlibs | |
| parent | 27c150bfcc222512a0f3816e72ee20285acad9b4 (diff) | |
| download | yosys-28bf712372c494043c7adc0de904925a9199c939.tar.gz yosys-28bf712372c494043c7adc0de904925a9199c939.tar.bz2 yosys-28bf712372c494043c7adc0de904925a9199c939.zip | |
Wrap arrival functions inside `YOSYS too
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 5e4529fd6..1cd4d2f30 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2241,6 +2241,7 @@ module DSP48E1 ( parameter [4:0] IS_INMODE_INVERTED = 5'b0; parameter [6:0] IS_OPMODE_INVERTED = 7'b0; +`ifdef YOSYS function integer \DSP48E1.P_arrival ; begin \DSP48E1.P_arrival = 0; @@ -2309,6 +2310,7 @@ module DSP48E1 ( // $error("Invalid DSP48E1 configuration"); end endfunction +`endif initial begin `ifndef YOSYS |