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* intel_alm: Fix illegal carry chainsgatecat2021-05-152-3/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add global buffer insertiongatecat2021-05-156-4/+78
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add IO buffer insertiongatecat2021-05-156-7/+127
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.Adam Greig2021-05-121-0/+22
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* Fix use of blif name in synth_xilinx commandMichael Christensen2021-04-271-1/+1
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* Add default assignments to other SB_* simulation modelsClaire Xenia Wolf2021-04-201-24/+44
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-201-1/+17
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* quicklogic: ABC9 synthesisLofty2021-04-176-5/+80
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* sf2: fix name of AND modulesStefan Riesenberger2021-04-091-3/+3
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* abc9: fix SCC issues (#2694)Eddie Hung2021-03-292-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* quicklogic: PolarPro 3 supportLofty2021-03-189-0/+770
| | | | | | | | Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
* Blackbox all whiteboxes after synthesisgatecat2021-03-1715-0/+15
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* memory_dff: Remove now-useless write port handling.Marcelina Kościelnicka2021-03-081-6/+7
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* Fix syntax error in adff2dff.vMarcelina Kościelnicka2021-02-241-1/+1
| | | | Fixes #2600.
* machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ↵William D. Jones2021-02-231-11/+5
| | | | values.
* machxo2: Add experimental status to help.William D. Jones2021-02-231-1/+1
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* machxo2: Add DCCA and DCMA blackbox primitives.William D. Jones2021-02-231-0/+17
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* machxo2: Fix reversed interpretation of REG_SD config bits.William D. Jones2021-02-231-2/+2
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* machxo2: Tristate is active-low.William D. Jones2021-02-232-5/+5
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* machxo2: Fix typos in FACADE_FF sim model.William D. Jones2021-02-231-5/+4
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* machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.William D. Jones2021-02-232-6/+6
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* machxo2: Improve help_mode output in synth_machxo2.William D. Jones2021-02-231-5/+5
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* machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires ↵William D. Jones2021-02-232-1/+17
| | | | to IO cells.
* machxo2: Add missing OSCH oscillator primitive.William D. Jones2021-02-231-0/+10
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* machxo2: Add -noiopad option to synth_machxo2.William D. Jones2021-02-231-2/+11
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* machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.William D. Jones2021-02-231-1/+1
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* machxo2: Fix cells_sim typo where OFX1 was multiply-driven.William D. Jones2021-02-231-1/+1
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* machxo2: synth_machxo2 now maps ports to FACADE_IO.William D. Jones2021-02-232-0/+12
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* machxo2: Add initial value for Q in FACADE_FF.William D. Jones2021-02-231-0/+2
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* machxo2: Add FACADE_IO simulation model. More comments on models.William D. Jones2021-02-231-0/+25
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* machxo2: Add FACADE_SLICE simulation model.William D. Jones2021-02-231-0/+83
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* machxo2: Improve FACADE_FF simulation model.William D. Jones2021-02-231-12/+20
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* machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.William D. Jones2021-02-232-4/+4
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* machxo2: Add dff.ys test, fix another cells_map.v typo.William D. Jones2021-02-231-1/+1
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* machxo2: Fix more oversights in machxo2 models. logic.ys test passes.William D. Jones2021-02-232-2/+6
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* machxo2: Fix typos. test/arch/run-test.sh passes.William D. Jones2021-02-232-2/+2
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* machxo2: Create basic techlibs and synth_machxo2 pass.William D. Jones2021-02-234-0/+320
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* Merge pull request #2585 from YosysHQ/dave/nexus-dotproductgatecat2021-02-121-0/+115
|\ | | | | nexus: Add MULTADDSUB9X9WIDE sim model
| * nexus: Add MULTADDSUB9X9WIDE sim modelDavid Shah2020-12-081-0/+115
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | verilog: significant block scoping improvementsZachary Snow2021-01-315-81/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* | xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-271-3/+3
| | | | | | | | | | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559.
* | xilinx: Add FDRSE_1, FDCPE_1.Marcelina Kościelnicka2021-01-271-0/+80
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* | Fix some trivial typos.Tom Verbeure2021-01-031-5/+5
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* | Merge pull request #2480 from YosysHQ/dave/nexus-lramwhitequark2021-01-015-1/+227
|\| | | | | nexus: Add LRAM inference
| * nexus: Add LRAM inferenceDavid Shah2020-12-075-1/+227
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | xilinx: Add some missing blackbox cells.Marcelina Kościelnicka2020-12-213-798/+6276
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* | xilinx: Regenerate cells_xtra.v using Vivado 2020.2Marcelina Kościelnicka2020-12-212-42/+49
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* | xilinx: Add FDDRCPE and FDDRRSE blackbox cells.Marcelina Kościelnicka2020-12-172-0/+33
|/ | | | | These are necessary primitives for proper DDR support on Virtex 2 and Spartan 3.
* nexus: More efficient CO mappingDavid Shah2020-12-021-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* add -noalu and -json option for apiculaPepijn de Vos2020-11-301-3/+32
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