| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | | | * | | | | | | | | | | | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 3 | -14/+28 | |
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| | | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 29 | -299/+1059 | |
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| | | | * | | | | | | | | | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 | |
| | | | * | | | | | | | | | | | Merge pull request #1289 from mmicko/anlogic_fixes | Clifford Wolf | 2019-08-22 | 5 | -91/+162 | |
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| | | | | * \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'upstream/master' into anlogic_fixes | Miodrag Milanovic | 2019-08-18 | 7 | -165/+37 | |
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| | | | | * | | | | | | | | | | | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 5 | -91/+162 | |
| | | | * | | | | | | | | | | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 | |
| | | | * | | | | | | | | | | | | Merge pull request #1281 from mmicko/efinix | Clifford Wolf | 2019-08-22 | 9 | -0/+798 | |
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| | | | | * | | | | | | | | | | | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
| | | | | * | | | | | | | | | | | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 | |
| | | | | * | | | | | | | | | | | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 | |
| | | | | * | | | | | | | | | | | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 | |
| | | | | * | | | | | | | | | | | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
| | | | | * | | | | | | | | | | | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 | |
| | | | | * | | | | | | | | | | | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 | |
| | | | | * | | | | | | | | | | | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 | |
| | | | | * | | | | | | | | | | | Merge remote-tracking branch 'upstream/master' into efinix | Miodrag Milanovic | 2019-08-09 | 9 | -267/+303 | |
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| | | | | * | | | | | | | | | | | | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 | |
| | | | | * | | | | | | | | | | | | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 | |
| | | | | * | | | | | | | | | | | | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 | |
| | | | | * | | | | | | | | | | | | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 | |
| | | | * | | | | | | | | | | | | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| | | * | | | | | | | | | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 6 | -283/+537 | |
| | | * | | | | | | | | | | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+1 | |
| | | * | | | | | | | | | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -18/+27 | |
| | | * | | | | | | | | | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 6 | -71/+220 | |
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| * | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 14 | -200/+97 | |
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| | * | | | | | | | | | | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 4 | -16/+19 | |
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| | | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 26 | -343/+629 | |
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| | | * | | | | | | | | | | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
| | | * | | | | | | | | | | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 | |
| | * | | | | | | | | | | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 3 | -19/+41 | |
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| | | * | | | | | | | | | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 3 | -6/+6 | |
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| | | * | | | | | | | | | | | Update abc_* attr in ecp5 and ice40 | Eddie Hung | 2019-08-16 | 2 | -11/+21 | |
| | | * | | | | | | | | | | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules | Eddie Hung | 2019-08-16 | 1 | -8/+20 | |
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| | * | | | | | | | | | | | Merge branch 'master' into eddie/pr1266_again | whitequark | 2019-08-18 | 1 | -15/+5 | |
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| | | * \ \ \ \ \ \ \ \ \ \ | Merge pull request #1250 from bwidawsk/master | Eddie Hung | 2019-08-16 | 1 | -15/+5 | |
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| | | | * | | | | | | | | | | techlibs/intel: Clean up Makefile | Ben Widawsky | 2019-08-05 | 1 | -15/+5 | |
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| | * | | | | | | | | | | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-12 | 1 | -1/+1 | |
| | * | | | | | | | | | | | Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad... | Eddie Hung | 2019-08-12 | 6 | -150/+32 | |
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| * | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-15 | 1 | -1/+5 | |
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| | * | | | | | | | | | | xilinx: Rework labels for faster Verilator testing | David Shah | 2019-08-13 | 1 | -1/+5 | |
| * | | | | | | | | | | | Only swap ports if $mul and not $__mul | Eddie Hung | 2019-08-13 | 1 | -1/+1 | |
| * | | | | | | | | | | | Add assign PCOUT = P to DSP48E1 | Eddie Hung | 2019-08-13 | 1 | -0/+2 | |
| * | | | | | | | | | | | Add DSP_A_MAXWIDTH_PARTIAL, refactor | Eddie Hung | 2019-08-13 | 2 | -145/+111 | |
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| * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 6 | -28/+50 | |
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| | * | | | | | | | | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 6 | -32/+150 | |
| | * | | | | | | | | | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 5 | -20/+14 | |
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| | | * | | | | | | | | | substr() -> compare() | Eddie Hung | 2019-08-07 | 1 | -3/+3 | |
| | | * | | | | | | | | | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -1/+1 | |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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