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Age
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*
Fixed small typo in ice40_unlut help summary
acw1251
2019-06-19
1
-1
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+1
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Fixed the help summary line for a few commands
acw1251
2019-06-19
1
-1
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+1
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ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
Simon Schubert
2019-06-10
1
-0
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+24
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Merge pull request #1073 from whitequark/ecp5-diamond-iob
David Shah
2019-06-06
1
-0
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+15
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ECP5: implement all Diamond I/O buffer primitives.
whitequark
2019-06-06
1
-0
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+15
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Remove extra newline
Eddie Hung
2019-06-03
1
-1
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+0
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Execute techmap and arith_map simultaneously
Eddie Hung
2019-06-03
1
-6
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+6
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Add "min bits" and "min wports" to xilinx dram rules
Eddie Hung
2019-05-23
1
-0
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+4
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Add "wreduce -keepdc", fixes #1016
Clifford Wolf
2019-05-20
1
-2
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+4
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ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
Sylvain Munaut
2019-05-13
1
-0
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+11
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Add "stat -tech xilinx"
Clifford Wolf
2019-05-11
1
-1
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+1
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Fix formatting for synth_intel.cc
Ben Widawsky
2019-05-09
1
-222
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+211
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Add "synth_xilinx -arch"
Clifford Wolf
2019-05-07
1
-1
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+13
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Merge remote-tracking branch 'origin/master' into clifford/specify
Eddie Hung
2019-05-03
6
-178
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+124
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Rename cells_map.v to prevent clash with ff_map.v
Eddie Hung
2019-05-03
1
-6
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+8
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Merge pull request #969 from YosysHQ/clifford/pmgenstuff
Clifford Wolf
2019-05-03
2
-0
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+4
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Run "peepopt" in generic "synth" pass and "synth_ice40"
Clifford Wolf
2019-04-30
2
-0
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+4
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Back to passing all xc7srl tests!
Eddie Hung
2019-05-01
1
-5
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+4
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
Eddie Hung
2019-05-01
3
-170
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+104
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Merge pull request #966 from YosysHQ/clifford/fix956
Clifford Wolf
2019-04-30
1
-1
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+1
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Add handling of init attributes in "opt_expr -undriven"
Clifford Wolf
2019-04-30
1
-1
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+1
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Refactor synth_xilinx to auto-generate doc
Eddie Hung
2019-04-26
1
-153
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+95
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Cleanup ice40
Eddie Hung
2019-04-26
1
-4
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+6
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WIP
Eddie Hung
2019-04-28
1
-36
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+22
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Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung
2019-04-28
2
-9
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+12
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Revert synth_xilinx 'fine' label more to how it used to be...
Eddie Hung
2019-04-26
1
-21
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+40
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Where did this check come from!?!
Eddie Hung
2019-04-26
1
-1
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+0
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Improve $specrule interface
Clifford Wolf
2019-04-23
1
-2
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+2
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Improve $specrule interface
Clifford Wolf
2019-04-23
1
-3
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+4
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Add $specrule cells for $setup/$hold/$skew specify rules
Clifford Wolf
2019-04-23
1
-0
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+28
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Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...
Clifford Wolf
2019-04-23
1
-70
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+70
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Add $specify2 and $specify3 cells to simlib
Clifford Wolf
2019-04-23
1
-0
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+147
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Update help message
Eddie Hung
2019-04-22
1
-1
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+1
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Move 'shregmap -tech xilinx' into map_cells
Eddie Hung
2019-04-22
1
-17
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+20
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Merge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung
2019-04-22
12
-21
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+480
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Merge pull request #941 from Wren6991/sim_lib_io_clke
Clifford Wolf
2019-04-22
1
-10
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+19
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ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware exp...
Luke Wren
2019-04-21
1
-10
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+19
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Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master
Clifford Wolf
2019-04-22
10
-10
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+458
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GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
Diego
2019-04-12
10
-11
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+459
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Re-added clean after techmap in synth_xilinx
Clifford Wolf
2019-04-22
1
-0
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+2
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Merge pull request #916 from YosysHQ/map_cells_before_map_luts
Clifford Wolf
2019-04-22
1
-10
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+10
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Merge pull request #911 from mmicko/gowin-nobram
Clifford Wolf
2019-04-22
1
-1
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+1
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Make nobram false by default for gowin
Miodrag Milanovic
2019-04-02
1
-1
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+1
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Tidy up, fix for -nosrl
Eddie Hung
2019-04-21
2
-12
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+16
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Merge branch 'map_cells_before_map_luts' into xc7srl
Eddie Hung
2019-04-21
1
-2
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+2
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Merge branch 'master' into map_cells_before_map_luts
Eddie Hung
2019-04-21
6
-59
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+85
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Add comments
Eddie Hung
2019-04-21
1
-0
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+7
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Use new pmux2shiftx from #944, remove my old attempt
Eddie Hung
2019-04-21
1
-3
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+8
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Merge remote-tracking branch 'origin' into xc7srl
Eddie Hung
2019-04-20
4
-44
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+69
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Revert "synth_* with -retime option now calls abc with -D 1 as well"
Eddie Hung
2019-04-18
11
-15
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+15
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