iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #941 from Wren6991/sim_lib_io_clke	Clifford Wolf	2019-04-22	1	-10/+19
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\| *	ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware exp...	Luke Wren	2019-04-21	1	-10/+19
* \|	Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master	Clifford Wolf	2019-04-22	10	-10/+458
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\| * \|	GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow	Diego	2019-04-12	10	-11/+459
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* \|	Re-added clean after techmap in synth_xilinx	Clifford Wolf	2019-04-22	1	-0/+2
* \|	Merge pull request #916 from YosysHQ/map_cells_before_map_luts	Clifford Wolf	2019-04-22	1	-10/+10
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\| * \	Merge branch 'master' into map_cells_before_map_luts	Eddie Hung	2019-04-21	6	-59/+85
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\| * \| \|	Missing techmap entry in help	Eddie Hung	2019-04-04	1	-0/+1
\| * \| \|	synth_xilinx to map_cells before map_luts	Eddie Hung	2019-04-04	1	-12/+12
* \| \| \|	Merge pull request #911 from mmicko/gowin-nobram	Clifford Wolf	2019-04-22	1	-1/+1
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\| * \| \|	Make nobram false by default for gowin	Miodrag Milanovic	2019-04-02	1	-1/+1
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* \| \|	Revert "synth_* with -retime option now calls abc with -D 1 as well"	Eddie Hung	2019-04-18	11	-15/+15
* \| \|	Merge branch 'master' into eddie/fix_retime	Eddie Hung	2019-04-18	4	-44/+69
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\| * \|	Merge pull request #928 from litghost/add_xc7_sim_models	Eddie Hung	2019-04-12	3	-41/+60
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\| \| * \|	Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.	Keith Rothman	2019-04-12	3	-52/+14
\| \| * \|	Fix LUT6_2 definition.	Keith Rothman	2019-04-09	1	-3/+3
\| \| * \|	Add additional cells sim models for core 7-series primatives.	Keith Rothman	2019-04-09	1	-0/+57
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\| * /	Fixing issues in CycloneV cell sim	Diego	2019-04-11	1	-3/+9
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* \|	synth_* with -retime option now calls abc with -D 1 as well	Eddie Hung	2019-04-10	11	-15/+15
* \|	Move techamp t:$_DFF_?N? to before abc call	Eddie Hung	2019-04-05	1	-2/+2
* \|	Retry	Eddie Hung	2019-04-05	1	-1/+1
* \|	Resolve @daveshah1 comment, update synth_xilinx help	Eddie Hung	2019-04-05	2	-7/+9
* \|	synth_xilinx to techmap FFs after abc call, otherwise -retime fails	Eddie Hung	2019-04-05	1	-3/+3
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*	xilinx: Add keep attribute where appropriate	David Shah	2019-03-22	2	-25/+31
*	Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873	Clifford Wolf	2019-03-19	1	-2/+4
*	Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes	Clifford Wolf	2019-03-12	1	-19/+0
*	Fix typo in ice40_braminit help msg	Clifford Wolf	2019-03-09	1	-1/+1
*	Merge pull request #859 from smunaut/ice40_braminit	Clifford Wolf	2019-03-09	4	-37/+212
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\| *	ice40: Run ice40_braminit pass by default	Sylvain Munaut	2019-03-08	1	-0/+1
\| *	ice40: Add ice40_braminit pass to allow initialization of BRAM from file	Sylvain Munaut	2019-03-08	3	-37/+211
* \|	Add link to SF2 / igloo2 macro library guide	Clifford Wolf	2019-03-07	1	-21/+24
* \|	Improvements in sf2 cells_sim.v	Clifford Wolf	2019-03-06	2	-30/+251
* \|	Add sf2 techmap rules for more FF types	Clifford Wolf	2019-03-06	1	-25/+39
* \|	Refactor SF2 iobuf insertion, Add clkint insertion	Clifford Wolf	2019-03-06	3	-83/+152
* \|	Improvements in SF2 flow and demo	Clifford Wolf	2019-03-05	2	-8/+23
* \|	Merge pull request #842 from litghost/merge_upstream	Clifford Wolf	2019-03-05	10	-176/+570
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\| * \|	Revert BRAM WRITE_MODE changes.	Keith Rothman	2019-03-04	1	-12/+12
\| * \|	Revert FF models to include IS_x_INVERTED parameters.	Keith Rothman	2019-03-01	1	-6/+34
\| * \|	Use singular for disabling of DRAM or BRAM inference.	Keith Rothman	2019-03-01	1	-13/+13
\| * \|	Modify arguments to match existing style.	Keith Rothman	2019-03-01	1	-6/+6
\| * \|	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	11	-221/+587
* \| \|	Merge pull request #850 from daveshah1/ecp5_warn_conflict	Clifford Wolf	2019-03-05	1	-2/+7
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\| * \| \|	ecp5: Demote conflicting FF init values to a warning	David Shah	2019-03-04	1	-2/+7
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* / /	Use "write_edif -pvector bra" for Xilinx EDIF files	Clifford Wolf	2019-03-05	1	-1/+1
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* \|	Fix ECP5 cells_sim for iverilog	Miodrag Milanovic	2019-03-01	1	-2/+3
* \|	Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode	Clifford Wolf	2019-02-28	1	-2/+2
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\| * \|	ice40: use 2 bits for READ/WRITE MODE for SB_RAM map	Elms	2019-02-28	1	-2/+2
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* \|	Reduce amount of trailing whitespace in code base	Larry Doolittle	2019-02-28	6	-19/+19
* \|	Merge pull request #794 from daveshah1/ecp5improve	Clifford Wolf	2019-02-28	7	-12/+388
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\| *	ecp5: Compatibility with Migen AsyncResetSynchronizer	David Shah	2019-02-25	2	-0/+20