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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 14:43:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 14:43:06 -0700 |
| commit | ff0912c75e2b15c02c9512466179e4b2a15eb3d1 (patch) | |
| tree | 38ffc7fdf9056aab9458167d510595c19316516d /techlibs | |
| parent | 19271bd996a79cb4be1db658fcf18227ee0a1dff (diff) | |
| download | yosys-ff0912c75e2b15c02c9512466179e4b2a15eb3d1.tar.gz yosys-ff0912c75e2b15c02c9512466179e4b2a15eb3d1.tar.bz2 yosys-ff0912c75e2b15c02c9512466179e4b2a15eb3d1.zip | |
synth_xilinx to techmap FFs after abc call, otherwise -retime fails
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 805ae8e6e..99c2be420 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -256,9 +256,9 @@ struct SynthXilinxPass : public Pass Pass::call(design, "opt -full"); if (vpr) { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); } else { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } Pass::call(design, "hierarchy -check"); @@ -269,7 +269,7 @@ struct SynthXilinxPass : public Pass { Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); - Pass::call(design, "techmap -map +/xilinx/lut_map.v"); + Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); } if (check_label(active, run_from, run_to, "map_cells")) |