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* namespace YosysClifford Wolf2014-09-272-2/+10
* Improvements in "synth" scriptClifford Wolf2014-09-181-8/+12
* Fixed $macc simlib model for zero-configClifford Wolf2014-09-161-1/+1
* Added "synth" commandClifford Wolf2014-09-142-0/+154
* Using alumacc in techmap.vClifford Wolf2014-09-141-237/+33
* Fixed simlib $macc model for xilinx xsimClifford Wolf2014-09-081-1/+15
* Simplified $fa undef modelClifford Wolf2014-09-081-1/+1
* Fixes and cleanups for blackbox.vClifford Wolf2014-09-082-70/+73
* Added $lcu cell typeClifford Wolf2014-09-082-74/+31
* Added "$fa" cell typeClifford Wolf2014-09-082-0/+28
* Using maccmap for $macc and $mul techmapClifford Wolf2014-09-071-190/+16
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-062-2/+2
* Added $macc SAT modelClifford Wolf2014-09-062-6/+6
* Added $macc simlib model (also use as techmap rule for now)Clifford Wolf2014-09-062-0/+172
* Removed $bu0 cell typeClifford Wolf2014-09-042-34/+5
* Undef-related fixes in simlib $alu modelClifford Wolf2014-09-021-3/+6
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-021-3/+2
* Fixed "test_cell -simlib all"Clifford Wolf2014-09-011-2/+3
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-311-0/+17
* Added $alu cell typeClifford Wolf2014-08-302-3/+47
* Replaced $__alu CO/CS outputs with full-width CO outputClifford Wolf2014-08-301-32/+28
* Using "via_celltype" in $mul carry-save-acc implementationClifford Wolf2014-08-181-34/+72
* Performance fix for new $__lcu techmap ruleClifford Wolf2014-08-181-7/+5
* Replaced recursive lcu scheme with bk adderClifford Wolf2014-08-181-61/+31
* Multiply using a carry-save accumulatorClifford Wolf2014-08-161-5/+45
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-0/+42
* Changes in techmap $__alu interfaceClifford Wolf2014-08-161-17/+17
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-152-29/+29
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-152-3/+3
* Simplified $__arraymul techmap ruleClifford Wolf2014-08-141-7/+13
* RIP $safe_pmuxClifford Wolf2014-08-142-64/+4
* Added techmap support for actual lookahead carry unitClifford Wolf2014-08-131-22/+73
* Preparations for lookahead ALU support in techmap.vClifford Wolf2014-08-131-28/+92
* New interface for $__alu in techmap.vClifford Wolf2014-08-131-129/+62
* Added adff2dff.v (for techmap -share_map)Clifford Wolf2014-08-072-1/+32
* Implemented recursive techmapClifford Wolf2014-08-031-1/+1
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-313-2/+6
* Reorganized stdcells.v (no actual code change, just moved and indented stuff)Clifford Wolf2014-07-311-747/+590
* Added techmap CONSTMAP featureClifford Wolf2014-07-301-2/+4
* New techmap default rules for $shr $sshr $shl $sshlClifford Wolf2014-07-301-282/+62
* Bugfix in simlib.v for iverilogClifford Wolf2014-07-291-5/+6
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-292-8/+112
* Added "make PRETTY=1"Clifford Wolf2014-07-242-12/+12
* Fixed simlib.v model for $memClifford Wolf2014-07-171-15/+15
* Updated simlib to new $mem/$memwr interfaceClifford Wolf2014-07-161-30/+55
* Added SIMLIB_NOLUT to simlib.vClifford Wolf2014-04-021-0/+2
* Added SIMLIB_NOSR to simlib.vClifford Wolf2014-04-021-0/+6
* Added support for dlatchsr cellsClifford Wolf2014-03-312-0/+136
* Merged addition of SED makefile variable from github.com/Siesh1oo/yosysClifford Wolf2014-03-111-1/+1
* Fixes for improved techmap of shifts with large B inputsClifford Wolf2014-03-061-8/+8