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| author | Clifford Wolf <clifford@clifford.at> | 2014-03-31 14:14:40 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-03-31 14:14:40 +0200 |
| commit | d4a1b0af5b41d1360c74a73fb2ae92ee5f6c3bd0 (patch) | |
| tree | 5a97ed0aa1a75d06f727e00bf37651eb6ee79d5c /techlibs | |
| parent | a3b9692a68e88bbe3e32e0dbbd30c5e20f3800b7 (diff) | |
| download | yosys-d4a1b0af5b41d1360c74a73fb2ae92ee5f6c3bd0.tar.gz yosys-d4a1b0af5b41d1360c74a73fb2ae92ee5f6c3bd0.tar.bz2 yosys-d4a1b0af5b41d1360c74a73fb2ae92ee5f6c3bd0.zip | |
Added support for dlatchsr cells
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simcells.v | 104 | ||||
| -rw-r--r-- | techlibs/common/simlib.v | 32 |
2 files changed, 136 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 10a809db6..5ecec7891 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -325,3 +325,107 @@ always @* begin end endmodule +module \$_DLATCHSR_NNN_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 0) + Q <= 0; + else if (S == 0) + Q <= 1; + else if (E == 0) + Q <= D; +end +endmodule + +module \$_DLATCHSR_NNP_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 1) + Q <= 0; + else if (S == 0) + Q <= 1; + else if (E == 0) + Q <= D; +end +endmodule + +module \$_DLATCHSR_NPN_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 0) + Q <= 0; + else if (S == 1) + Q <= 1; + else if (E == 0) + Q <= D; +end +endmodule + +module \$_DLATCHSR_NPP_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 1) + Q <= 0; + else if (S == 1) + Q <= 1; + else if (E == 0) + Q <= D; +end +endmodule + +module \$_DLATCHSR_PNN_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 0) + Q <= 0; + else if (S == 0) + Q <= 1; + else if (E == 1) + Q <= D; +end +endmodule + +module \$_DLATCHSR_PNP_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 1) + Q <= 0; + else if (S == 0) + Q <= 1; + else if (E == 1) + Q <= D; +end +endmodule + +module \$_DLATCHSR_PPN_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 0) + Q <= 0; + else if (S == 1) + Q <= 1; + else if (E == 1) + Q <= D; +end +endmodule + +module \$_DLATCHSR_PPP_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == 1) + Q <= 0; + else if (S == 1) + Q <= 1; + else if (E == 1) + Q <= D; +end +endmodule + diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 4436abfe7..908314f84 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1097,6 +1097,38 @@ endmodule // -------------------------------------------------------- +module \$dlatchsr (EN, SET, CLR, D, Q); + +parameter WIDTH = 0; +parameter EN_POLARITY = 1'b1; +parameter SET_POLARITY = 1'b1; +parameter CLR_POLARITY = 1'b1; + +input EN; +input [WIDTH-1:0] SET, CLR, D; +output reg [WIDTH-1:0] Q; + +wire pos_en = EN == EN_POLARITY; +wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET; +wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR; + +genvar i; +generate + for (i = 0; i < WIDTH; i = i+1) begin:bit + always @* + if (pos_clr[i]) + Q[i] <= 0; + else if (pos_set[i]) + Q[i] <= 1; + else if (pos_en) + Q[i] <= D[i]; + end +endgenerate + +endmodule + +// -------------------------------------------------------- + module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT); parameter NAME = ""; |