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abc9_ops: use TimingInfo for -prep_{lut,box} too
Eddie Hung
2020-02-27
1
-7
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+10
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Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy
Eddie Hung
2020-02-27
1
-14
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+12
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ice40: fix specify for inverted clocks
Eddie Hung
2020-02-27
1
-27
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+27
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Fix tests by gating some specify constructs from iverilog
Eddie Hung
2020-02-27
1
-0
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+16
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abc9_ops: ignore (* abc9_flop *) if not '-dff'
Eddie Hung
2020-02-27
1
-2
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+6
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ice40: specify fixes
Eddie Hung
2020-02-27
3
-66
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+66
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ice40: move over to specify blocks for -abc9
Eddie Hung
2020-02-27
10
-164
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+1344
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synth_ecp5: use +/abc9_model.v
Eddie Hung
2020-02-27
1
-1
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+1
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Update xilinx for ABC9
Eddie Hung
2020-02-27
3
-20
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+16
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Create +/abc9_model.v for $__ABC9_{DELAY,FF_}
Eddie Hung
2020-02-27
2
-0
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+11
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ecp5: remove small LUT entries
Eddie Hung
2020-02-27
1
-24
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+6
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Fix commented out specify statement
Eddie Hung
2020-02-27
1
-6
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+6
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xilinx: improve specify functionality
Eddie Hung
2020-02-27
5
-446
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+519
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ecp5: deprecate abc9_{arrival,required} and *.{lut,box}
Eddie Hung
2020-02-27
7
-86
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+120
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xilinx: use specify blocks in place of abc9_{arrival,required}
Eddie Hung
2020-02-27
1
-176
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+404
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Auto-generate .box/.lut files from specify blocks
Eddie Hung
2020-02-27
7
-426
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+151
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abc9_ops: -prep_box, to be called once
Eddie Hung
2020-02-27
1
-1
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+1
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abc9_ops: -prep_lut and -write_lut to auto-generate LUT library
Eddie Hung
2020-02-27
2
-4
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+85
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coolrunner2: Attempt to give wires/cells more meaningful names
R. Ou
2020-03-02
2
-23
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+66
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coolrunner2: Fix invalid multiple fanouts of XOR/OR gates
R. Ou
2020-03-02
1
-0
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+96
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coolrunner2: Fix packed register+input buffer insertion
R. Ou
2020-03-02
1
-2
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+84
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coolrunner2: Insert many more required feedthrough cells
R. Ou
2020-03-01
3
-102
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+215
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Merge pull request #1709 from rqou/coolrunner2_counter
Claire Wolf
2020-02-27
3
-0
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+165
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coolrunner2: Use extract_counter to optimize counters
R. Ou
2020-02-17
3
-0
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+165
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Merge pull request #1708 from rqou/coolrunner2-buf-fix
Claire Wolf
2020-02-27
4
-54
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+163
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coolrunner2: Separate and improve buffer cell insertion pass
R. Ou
2020-02-16
4
-54
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+163
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xilinx: mark IOBUFDSE3 IOB pin as external
Piotr Binkowski
2020-02-27
2
-1
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+2
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Remove executable flag from files
Miodrag Milanovic
2020-02-15
5
-0
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+0
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abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr
Eddie Hung
2020-02-13
1
-11
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+12
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abc9: cleanup
Eddie Hung
2020-02-10
1
-40
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+40
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Remove unnecessary comma
Eddie Hung
2020-02-07
1
-3
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+2
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techmap: fix shiftx2mux decomposition
Eddie Hung
2020-02-07
1
-8
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+6
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xilinx: Add support for LUT RAM on LUT4-based devices.
Marcin Kościelnicki
2020-02-07
4
-27
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+22
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xilinx: Initial support for LUT4 devices.
Marcin Kościelnicki
2020-02-07
3
-53
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+152
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Merge pull request #1685 from dh73/gowin
Eddie Hung
2020-02-06
1
-1
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+1
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Removing cells_sim.v from bram techmap pass
Diego H
2020-02-06
1
-1
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+1
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
Marcin Kościelnicki
2020-02-07
11
-1
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+370
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xilinx: Add support for Spartan 3A DSP block RAMs.
Marcin Kościelnicki
2020-02-07
3
-1
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+39
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Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map
Eddie Hung
2020-02-06
1
-109
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+43
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Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk
Eddie Hung
2020-02-06
1
-4
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+5
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Fix/cleanup +/xilinx/arith_map.v
Eddie Hung
2020-02-06
1
-111
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+44
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synth_*: call 'opt -fast' after 'techmap'
Eddie Hung
2020-02-05
8
-5
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+9
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shiftx2mux: fix select out of bounds
Eddie Hung
2020-02-05
1
-1
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+2
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Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
Eddie Hung
2020-02-05
24
-359
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+1041
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Merge pull request #1661 from YosysHQ/eddie/abc9_required
Eddie Hung
2020-02-05
7
-144
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+375
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Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
Eddie Hung
2020-01-27
5
-129
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+99
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Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req...
Eddie Hung
2020-01-15
1
-1
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+1
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abc9_ops: -write_box is empty, output a dummy box to prevent ABC error
Eddie Hung
2020-01-15
2
-2
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+0
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abc9_ops: generate flop box ids, add abc9_required to FD* cells
Eddie Hung
2020-01-14
1
-12
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+45
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Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req...
Eddie Hung
2020-01-14
3
-23
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+30
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