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author | Eddie Hung <eddie@fpgeh.com> | 2020-02-10 10:17:23 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-10 10:17:23 -0800 |
commit | c244b27b6db72b5341186f732c8fba030c177164 (patch) | |
tree | dfbd7400eb55c5b2dc8bb8b3595ea4350197d67d /techlibs | |
parent | d4ff5b2d007c73cd95fa61bafdb65a47796014d9 (diff) | |
download | yosys-c244b27b6db72b5341186f732c8fba030c177164.tar.gz yosys-c244b27b6db72b5341186f732c8fba030c177164.tar.bz2 yosys-c244b27b6db72b5341186f732c8fba030c177164.zip |
abc9: cleanup
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/xilinx/abc9_map.v | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 7dc027176..539fa4547 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -215,11 +215,11 @@ module FDCE (output Q, (* techmap_autopurge *) input C, CE, D, CLR); .IS_PRE_INVERTED(IS_CLR_INVERTED) ) _TECHMAP_REPLACE_ ( .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC1 below + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC1 below ); // Since this is an async flop, async behaviour is dealt with here $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); @@ -233,11 +233,11 @@ module FDCE (output Q, (* techmap_autopurge *) input C, CE, D, CLR); .IS_CLR_INVERTED(IS_CLR_INVERTED) ) _TECHMAP_REPLACE_ ( .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC0 below + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC0 below ); // Since this is an async flop, async behaviour is dealt with here $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); @@ -258,11 +258,11 @@ module FDCE_1 (output Q, (* techmap_autopurge *) input C, CE, D, CLR); .INIT(1'b0) ) _TECHMAP_REPLACE_ ( .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC1 below + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC1 below ); $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR), .Y(QQ)); end @@ -272,11 +272,11 @@ module FDCE_1 (output Q, (* techmap_autopurge *) input C, CE, D, CLR); .INIT(1'b0) ) _TECHMAP_REPLACE_ ( .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC0 below + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC0 below ); $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR), .Y(QQ)); end endgenerate @@ -303,11 +303,11 @@ module FDPE (output Q, (* techmap_autopurge *) input C, CE, D, PRE); .IS_CLR_INVERTED(IS_PRE_INVERTED), ) _TECHMAP_REPLACE_ ( .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC0 below + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC0 below ); $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); end @@ -320,11 +320,11 @@ module FDPE (output Q, (* techmap_autopurge *) input C, CE, D, PRE); .IS_PRE_INVERTED(IS_PRE_INVERTED), ) _TECHMAP_REPLACE_ ( .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC1 below + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC1 below ); $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); end endgenerate @@ -344,11 +344,11 @@ module FDPE_1 (output Q, (* techmap_autopurge *) input C, CE, D, PRE); .INIT(1'b0) ) _TECHMAP_REPLACE_ ( .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC0 below + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC0 below ); $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE), .Y(QQ)); end @@ -358,11 +358,11 @@ module FDPE_1 (output Q, (* techmap_autopurge *) input C, CE, D, PRE); .INIT(1'b0) ) _TECHMAP_REPLACE_ ( .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC1 below + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC1 below ); $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE), .Y(QQ)); end endgenerate |