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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-06 13:51:23 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-06 13:51:23 -0800 |
| commit | 1784d25f53abaf4b457e180af49dddca8718d88d (patch) | |
| tree | 892b1a9b6f694bb117c0c5717fc3e36b5505fc70 /techlibs | |
| parent | 8f559b070ab9e27df3f8c5022c0b108bc2a53534 (diff) | |
| parent | d625e399cb0b30d4a64085772f5f6d6011dfc0fd (diff) | |
| download | yosys-1784d25f53abaf4b457e180af49dddca8718d88d.tar.gz yosys-1784d25f53abaf4b457e180af49dddca8718d88d.tar.bz2 yosys-1784d25f53abaf4b457e180af49dddca8718d88d.zip | |
Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map
Fix/cleanup +/xilinx/arith_map.v
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/arith_map.v | 152 |
1 files changed, 43 insertions, 109 deletions
diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index 40c378d16..4ae938827 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -53,63 +53,31 @@ module _80_xilinx_lcu (P, G, CI, CO); localparam MAX_WIDTH = CARRY4_COUNT * 4; localparam PAD_WIDTH = MAX_WIDTH - WIDTH; - wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G}; - wire [MAX_WIDTH-1:0] C = CO; + wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G}; + wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G}; + wire [MAX_WIDTH-1:0] C; + assign CO = C; generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice - - // Partially occupied CARRY4 - if ((i+1)*4 > WIDTH) begin - - // First one - if (i == 0) begin - CARRY4 carry4_1st_part - ( - .CYINIT(CI), - .CI (1'd0), - .DI (G [(WIDTH - 1):i*4]), - .S (S [(WIDTH - 1):i*4]), - .CO (CO[(WIDTH - 1):i*4]), - ); - // Another one - end else begin - CARRY4 carry4_part - ( - .CYINIT(1'd0), - .CI (C [i*4 - 1]), - .DI (G [(WIDTH - 1):i*4]), - .S (S [(WIDTH - 1):i*4]), - .CO (CO[(WIDTH - 1):i*4]), - ); - end - - // Fully occupied CARRY4 + if (i == 0) begin + CARRY4 carry4 + ( + .CYINIT(CI), + .CI (1'd0), + .DI (GG[i*4 +: 4]), + .S (S [i*4 +: 4]), + .CO (C [i*4 +: 4]), + ); end else begin - - // First one - if (i == 0) begin - CARRY4 carry4_1st_full - ( - .CYINIT(CI), - .CI (1'd0), - .DI (G [((i+1)*4 - 1):i*4]), - .S (S [((i+1)*4 - 1):i*4]), - .CO (CO[((i+1)*4 - 1):i*4]), - ); - // Another one - end else begin - CARRY4 carry4_full - ( - .CYINIT(1'd0), - .CI (C [i*4 - 1]), - .DI (G [((i+1)*4 - 1):i*4]), - .S (S [((i+1)*4 - 1):i*4]), - .CO (CO[((i+1)*4 - 1):i*4]), - ); - end - + CARRY4 carry4 + ( + .CYINIT(1'd0), + .CI (C [i*4 - 1]), + .DI (GG[i*4 +: 4]), + .S (S [i*4 +: 4]), + .CO (C [i*4 +: 4]), + ); end - end endgenerate `endif @@ -254,67 +222,33 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB}; wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB}; - wire [MAX_WIDTH-1:0] C = CO; + wire [MAX_WIDTH-1:0] O; + wire [MAX_WIDTH-1:0] C; + assign Y = O, CO = C; genvar i; generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice - - // Partially occupied CARRY4 - if ((i+1)*4 > Y_WIDTH) begin - - // First one - if (i == 0) begin - CARRY4 carry4_1st_part - ( - .CYINIT(CI), - .CI (1'd0), - .DI (DI[(Y_WIDTH - 1):i*4]), - .S (S [(Y_WIDTH - 1):i*4]), - .O (Y [(Y_WIDTH - 1):i*4]), - .CO (CO[(Y_WIDTH - 1):i*4]) - ); - // Another one - end else begin - CARRY4 carry4_part - ( - .CYINIT(1'd0), - .CI (C [i*4 - 1]), - .DI (DI[(Y_WIDTH - 1):i*4]), - .S (S [(Y_WIDTH - 1):i*4]), - .O (Y [(Y_WIDTH - 1):i*4]), - .CO (CO[(Y_WIDTH - 1):i*4]) - ); - end - - // Fully occupied CARRY4 + if (i == 0) begin + CARRY4 carry4 + ( + .CYINIT(CI), + .CI (1'd0), + .DI (DI[i*4 +: 4]), + .S (S [i*4 +: 4]), + .O (O [i*4 +: 4]), + .CO (C [i*4 +: 4]) + ); end else begin - - // First one - if (i == 0) begin - CARRY4 carry4_1st_full - ( - .CYINIT(CI), - .CI (1'd0), - .DI (DI[((i+1)*4 - 1):i*4]), - .S (S [((i+1)*4 - 1):i*4]), - .O (Y [((i+1)*4 - 1):i*4]), - .CO (CO[((i+1)*4 - 1):i*4]) - ); - // Another one - end else begin - CARRY4 carry4_full - ( - .CYINIT(1'd0), - .CI (C [i*4 - 1]), - .DI (DI[((i+1)*4 - 1):i*4]), - .S (S [((i+1)*4 - 1):i*4]), - .O (Y [((i+1)*4 - 1):i*4]), - .CO (CO[((i+1)*4 - 1):i*4]) - ); - end - + CARRY4 carry4 + ( + .CYINIT(1'd0), + .CI (C [i*4 - 1]), + .DI (DI[i*4 +: 4]), + .S (S [i*4 +: 4]), + .O (O [i*4 +: 4]), + .CO (C [i*4 +: 4]) + ); end - end endgenerate `endif |