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| author | Piotr Binkowski <pbinkowski@antmicro.com> | 2020-02-27 11:21:01 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-02-27 13:15:57 +0100 |
| commit | 62ab100c611071a41de5ff1ab0bd482b9c7bcc82 (patch) | |
| tree | 9f22d3ca4e8e26dc18bac8527e9bf0f9286fd42a /techlibs | |
| parent | 036c46de1e6442a31aac8d00c5f7cdf99c247a5b (diff) | |
| download | yosys-62ab100c611071a41de5ff1ab0bd482b9c7bcc82.tar.gz yosys-62ab100c611071a41de5ff1ab0bd482b9c7bcc82.tar.bz2 yosys-62ab100c611071a41de5ff1ab0bd482b9c7bcc82.zip | |
xilinx: mark IOBUFDSE3 IOB pin as external
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.py | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_xtra.v | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 75646f594..631664d67 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -376,7 +376,7 @@ CELLS = [ Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), # Output. # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}), Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index e87f4ec76..a779bcae0 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -7559,6 +7559,7 @@ module IOBUFDSE3 (...); output O; (* iopad_external_pin *) inout IO; + (* iopad_external_pin *) inout IOB; input DCITERMDISABLE; input I; |