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Author
Age
Files
Lines
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Fix ECP5 cells_sim for iverilog
Miodrag Milanovic
2019-03-01
1
-2
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+3
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Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
Clifford Wolf
2019-02-28
1
-2
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+2
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ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
Elms
2019-02-28
1
-2
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+2
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Reduce amount of trailing whitespace in code base
Larry Doolittle
2019-02-28
6
-19
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+19
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Merge pull request #794 from daveshah1/ecp5improve
Clifford Wolf
2019-02-28
7
-12
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+388
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ecp5: Compatibility with Migen AsyncResetSynchronizer
David Shah
2019-02-25
2
-0
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+20
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ecp5: Add DDRDLLA
David Shah
2019-02-19
1
-0
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+9
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ecp5: Add DELAYF/DELAYG blackboxes
David Shah
2019-02-19
1
-0
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+18
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ecp5: Add ECLKSYNCB blackbox
David Shah
2019-02-13
1
-1
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+7
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ecp5: Full set of IO-related blackboxes
David Shah
2019-02-12
1
-0
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+102
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ecp5: Support for flipflop initialisation
David Shah
2019-01-22
3
-4
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+199
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ecp5: Add LSRMODE to flipflops for PRLD support
David Shah
2019-01-21
1
-7
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+16
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ecp5: More blackboxes
David Shah
2019-01-21
1
-0
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+17
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ecp5: Increase threshold for ALU mapping
David Shah
2019-01-21
1
-1
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+1
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techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
Larry Doolittle
2019-02-26
1
-22
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+22
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Clean up some whitepsace outliers
Larry Doolittle
2019-02-26
1
-2
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+2
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Merge pull request #740 from daveshah1/improve_dress
Clifford Wolf
2019-02-22
2
-3
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+3
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ecp5: Use abc -dress
David Shah
2019-02-06
1
-2
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+2
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ice40: Use abc -dress in synth_ice40
David Shah
2019-02-06
1
-1
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+1
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Bugfix in ice40_dsp
Clifford Wolf
2019-02-21
2
-20
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+33
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Add ice40 test_dsp_map test case generator
Clifford Wolf
2019-02-20
2
-0
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+99
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Add "synth_ice40 -dsp"
Clifford Wolf
2019-02-20
1
-3
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+27
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Improve iCE40 SB_MAC16 model
Clifford Wolf
2019-02-20
5
-121
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+179
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Add first draft of functional SB_MAC16 model
Clifford Wolf
2019-02-19
4
-53
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+467
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Fixed Anlogic simulation model
Miodrag Milanovic
2019-01-25
1
-1
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+1
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Add SF2 IO buffer insertion
Clifford Wolf
2019-01-17
4
-1
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+168
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Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
Clifford Wolf
2019-01-17
1
-2
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+17
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Merge pull request #777 from mmicko/achronix_cell_sim_fix
Clifford Wolf
2019-01-04
1
-1
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+1
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Fix cells_sim.v for Achronix FPGA
Miodrag Milanovic
2019-01-04
1
-1
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+1
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Unify usage of noflatten among architectures
Miodrag Milanovic
2019-01-04
4
-8
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+16
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Merge pull request #755 from Icenowy/anlogic-dram-init
Clifford Wolf
2019-01-02
6
-2
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+96
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anlogic: implement DRAM initialization
Icenowy Zheng
2018-12-20
6
-2
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+96
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Merge pull request #750 from Icenowy/anlogic-ff-init
Clifford Wolf
2019-01-02
2
-14
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+15
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anlogic: set the init value of DFFs
Icenowy Zheng
2018-12-18
2
-14
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+15
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Merge pull request #772 from whitequark/synth_lut
Clifford Wolf
2019-01-02
2
-7
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+41
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synth_ice40: use 4-LUT coarse synthesis mode.
whitequark
2019-01-02
1
-1
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+1
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synth: add k-LUT mode.
whitequark
2019-01-02
1
-2
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+36
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synth: improve script documentation. NFC.
whitequark
2019-01-02
1
-6
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+6
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Merge pull request #771 from whitequark/techmap_cmp2lut
Clifford Wolf
2019-01-02
2
-1
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+106
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cmp2lut: new techmap pass.
whitequark
2019-01-02
2
-1
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+106
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Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
15
-22
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+22
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Merge pull request #766 from Icenowy/anlogic-latches
Clifford Wolf
2018-12-31
1
-0
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+12
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anlogic: add latch cells
Icenowy Zheng
2018-12-25
1
-0
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+12
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Fix 7 instances of add_share_file to add_gen_share_file
Larry Doolittle
2018-12-29
1
-8
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+8
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Merge pull request #752 from Icenowy/anlogic-lut-cost
Clifford Wolf
2018-12-19
1
-1
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+1
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Anlogic: let LUT5/6 have more cost than LUT4-
Icenowy Zheng
2018-12-19
1
-1
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+1
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Merge pull request #753 from Icenowy/anlogic-makefile-fix
Clifford Wolf
2018-12-19
1
-0
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+1
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anlogic: fix Makefile.inc
Icenowy Zheng
2018-12-19
1
-0
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+1
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anlogic: fix dbits of Anlogic Eagle DRAM16X4
Icenowy Zheng
2018-12-18
1
-1
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+1
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anlogic: add support for Eagle Distributed RAM
Icenowy Zheng
2018-12-17
4
-1
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+43
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