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* Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
* Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_modeClifford Wolf2019-02-281-2/+2
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| * ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
* | Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-286-19/+19
* | Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-287-12/+388
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| * ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-252-0/+20
| * ecp5: Add DDRDLLADavid Shah2019-02-191-0/+9
| * ecp5: Add DELAYF/DELAYG blackboxesDavid Shah2019-02-191-0/+18
| * ecp5: Add ECLKSYNCB blackboxDavid Shah2019-02-131-1/+7
| * ecp5: Full set of IO-related blackboxesDavid Shah2019-02-121-0/+102
| * ecp5: Support for flipflop initialisationDavid Shah2019-01-223-4/+199
| * ecp5: Add LSRMODE to flipflops for PRLD supportDavid Shah2019-01-211-7/+16
| * ecp5: More blackboxesDavid Shah2019-01-211-0/+17
| * ecp5: Increase threshold for ALU mappingDavid Shah2019-01-211-1/+1
* | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut moduleLarry Doolittle2019-02-261-22/+22
* | Clean up some whitepsace outliersLarry Doolittle2019-02-261-2/+2
* | Merge pull request #740 from daveshah1/improve_dressClifford Wolf2019-02-222-3/+3
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| * | ecp5: Use abc -dressDavid Shah2019-02-061-2/+2
| * | ice40: Use abc -dress in synth_ice40David Shah2019-02-061-1/+1
* | | Bugfix in ice40_dspClifford Wolf2019-02-212-20/+33
* | | Add ice40 test_dsp_map test case generatorClifford Wolf2019-02-202-0/+99
* | | Add "synth_ice40 -dsp"Clifford Wolf2019-02-201-3/+27
* | | Improve iCE40 SB_MAC16 modelClifford Wolf2019-02-205-121/+179
* | | Add first draft of functional SB_MAC16 modelClifford Wolf2019-02-194-53/+467
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* / Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
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* Add SF2 IO buffer insertionClifford Wolf2019-01-174-1/+168
* Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
* Merge pull request #777 from mmicko/achronix_cell_sim_fixClifford Wolf2019-01-041-1/+1
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| * Fix cells_sim.v for Achronix FPGAMiodrag Milanovic2019-01-041-1/+1
* | Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-044-8/+16
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* Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
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| * anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
* | Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-022-14/+15
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| * | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
* | | Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-022-7/+41
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| * | | synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
| * | | synth: add k-LUT mode.whitequark2019-01-021-2/+36
| * | | synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
* | | | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-022-1/+106
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| * | | cmp2lut: new techmap pass.whitequark2019-01-022-1/+106
* | | | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-0215-22/+22
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* | | Merge pull request #766 from Icenowy/anlogic-latchesClifford Wolf2018-12-311-0/+12
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| * | | anlogic: add latch cellsIcenowy Zheng2018-12-251-0/+12
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* / | Fix 7 instances of add_share_file to add_gen_share_fileLarry Doolittle2018-12-291-8/+8
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* | Merge pull request #752 from Icenowy/anlogic-lut-costClifford Wolf2018-12-191-1/+1
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| * | Anlogic: let LUT5/6 have more cost than LUT4-Icenowy Zheng2018-12-191-1/+1
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* | Merge pull request #753 from Icenowy/anlogic-makefile-fixClifford Wolf2018-12-191-0/+1
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| * | anlogic: fix Makefile.incIcenowy Zheng2018-12-191-0/+1
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* / anlogic: fix dbits of Anlogic Eagle DRAM16X4Icenowy Zheng2018-12-181-1/+1
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* anlogic: add support for Eagle Distributed RAMIcenowy Zheng2018-12-174-1/+43