iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fitting help messages to 80 character width	KrystalDelusion	2022-08-24	1	-3/+4
*	xilinx: Use `memory_libmap` pass.	Marcelina Kościelnicka	2022-05-18	37	-2269/+4525
*	xilinx: Add RAMB4* blackboxes	Marcelina Kościelnicka	2022-03-21	2	-1/+695
*	iopadmap: Add native support for negative-polarity output enable.	Marcelina Kościelnicka	2021-11-09	2	-10/+3
*	Fixes xc7 BRAM36s	Maciej Dudek	2021-07-30	1	-4/+6
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	9	-9/+9
*	Fix use of blif name in synth_xilinx command	Michael Christensen	2021-04-27	1	-1/+1
*	Blackbox all whiteboxes after synthesis	gatecat	2021-03-17	1	-0/+1
*	verilog: significant block scoping improvements	Zachary Snow	2021-01-31	1	-2/+4
*	xilinx_dffopt: Don't crash on missing IS_*_INVERTED.	Marcelina Kościelnicka	2021-01-27	1	-3/+3
*	xilinx: Add FDRSE_1, FDCPE_1.	Marcelina Kościelnicka	2021-01-27	1	-0/+80
*	xilinx: Add some missing blackbox cells.	Marcelina Kościelnicka	2020-12-21	3	-798/+6276
*	xilinx: Regenerate cells_xtra.v using Vivado 2020.2	Marcelina Kościelnicka	2020-12-21	2	-42/+49
*	xilinx: Add FDDRCPE and FDDRRSE blackbox cells.	Marcelina Kościelnicka	2020-12-17	2	-0/+33
*	Move signal declarations to before first use	Jeff Goeders	2020-10-19	1	-2/+2
*	xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)	Eddie Hung	2020-09-23	2	-17/+65
*	Replace opt_rmdff with opt_dff.	Marcelina Kościelnicka	2020-08-07	1	-3/+1
*	opt_expr: Remove -clkinv option, make it the default.	Marcelina Kościelnicka	2020-07-31	1	-1/+1
*	synth_xilinx: Use opt_dff.	Marcelina Kościelnicka	2020-07-30	1	-17/+12
*	Remove EXPLICIT_CARRY logic.	Keith Rothman	2020-07-23	3	-150/+2
*	xilinx: Fix srl regression.	Marcelina Kościelnicka	2020-07-12	1	-2/+2
*	xilinx: Use dfflegalize.	Marcelina Kościelnicka	2020-07-09	6	-484/+131
*	Update dff2dffe, dff2dffs, zinit to new FF types.	Marcelina Kościelnicka	2020-06-23	4	-50/+50
*	Use C++11 final/override keywords.	whitequark	2020-06-18	2	-7/+7
*	xilinx: tidy up cells_sim.v a little	Eddie Hung	2020-05-25	1	-5/+7
*	Add force_downto and force_upto wire attributes.	Marcelina Kościelnicka	2020-05-19	4	-0/+33
*	xilinx: gate specify/attributes from iverilog	Eddie Hung	2020-05-14	1	-1/+3
*	xilinx/ice40/ecp5: zinit requires selected wires, so select them all	Eddie Hung	2020-05-14	1	-2/+2
*	xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells	Eddie Hung	2020-05-14	1	-1/+19
*	abc9_ops: add -prep_bypass for auto bypass boxes; refactor	Eddie Hung	2020-05-14	6	-761/+127
*	synth_*: no need to explicitly read +/abc9_model.v	Eddie Hung	2020-05-14	1	-1/+1
*	abc9_ops: -prep_dff_map to error if async flop found	Eddie Hung	2020-05-14	1	-4/+0
*	Uncomment negative setup times; clamp to zero for connectivity	Eddie Hung	2020-05-14	1	-13/+29
*	synth_xilinx: rename dff_mode -> dff	Eddie Hung	2020-05-14	1	-8/+10
*	abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes	Eddie Hung	2020-05-14	4	-366/+5
*	synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad	Eddie Hung	2020-05-04	1	-3/+5
*	xilinx: improve xilinx_dffopt message	Eddie Hung	2020-04-22	1	-3/+6
*	Use default parameter value in getParam	Marcelina Kościelnicka	2020-04-21	1	-3/+3
*	Get rid of dffsr2dff.	Marcelina Kościelnicka	2020-04-15	1	-2/+1
*	Merge pull request #1648 from YosysHQ/eddie/cmp2lcu	Eddie Hung	2020-04-03	1	-2/+1
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\| *	synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'	Eddie Hung	2020-04-03	1	-2/+1
* \|	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-13/+13
\|/
*	xilinx: Mark IOBUFDS.IOB as external pad	Marcin Kościelnicki	2020-03-20	2	-1/+2
*	xilinx: consider DSP48E1.ADREG	Eddie Hung	2020-03-04	4	-5/+8
*	xilinx: cleanup DSP48E1 handling for abc9	Eddie Hung	2020-03-04	3	-86/+125
*	xilinx: improve specify for DSP48E1	Eddie Hung	2020-03-04	1	-32/+116
*	xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v	Eddie Hung	2020-03-04	2	-5/+14
*	Remove RAMB{18,36}E1 from cells_xtra.py	Eddie Hung	2020-02-27	1	-2/+2
*	xilinx: Update RAMB* specify entries	Eddie Hung	2020-02-27	1	-11/+42
*	xilinx: add delays to INV	Eddie Hung	2020-02-27	1	-0/+3