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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 10:25:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 8fbb55f4aba9ccb850680dc9c7ab582e8c964a4a (patch) | |
| tree | 33edc1fef5c872cb917086bcd6354501285c2258 /techlibs/xilinx | |
| parent | 63246a5c0eb5780675384d00443e6e46b5e59603 (diff) | |
| download | yosys-8fbb55f4aba9ccb850680dc9c7ab582e8c964a4a.tar.gz yosys-8fbb55f4aba9ccb850680dc9c7ab582e8c964a4a.tar.bz2 yosys-8fbb55f4aba9ccb850680dc9c7ab582e8c964a4a.zip | |
synth_*: no need to explicitly read +/abc9_model.v
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c45d389ef..d6ca9e57e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -616,7 +616,7 @@ struct SynthXilinxPass : public ScriptPass log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " "will use timing for 'xc7' instead.\n", family.c_str()); run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); - run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v"); + run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v"); std::string abc9_opts; std::string k = "synth_xilinx.abc9.W"; if (active_design && active_design->scratchpad.count(k)) |