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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 10:32:51 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 11:31:12 -0800 |
| commit | 78d4fff69d09f46f1777213116f09826ba008991 (patch) | |
| tree | ea8424b1474f0967926feb637352f7026a69bae5 /techlibs/xilinx | |
| parent | 968956badb977984133b00c38d0a08f3e2d0b854 (diff) | |
| download | yosys-78d4fff69d09f46f1777213116f09826ba008991.tar.gz yosys-78d4fff69d09f46f1777213116f09826ba008991.tar.bz2 yosys-78d4fff69d09f46f1777213116f09826ba008991.zip | |
xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc9_map.v | 11 | ||||
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 8 |
2 files changed, 14 insertions, 5 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 53d9a3c9a..5d21bac07 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -777,6 +777,7 @@ module DSP48E1 ( wire [17:0] $B; wire [47:0] $C; wire [24:0] $D; + wire [47:0] $PCIN; if (PREG == 0) begin if (MREG == 0 && AREG == 0) assign $A = A; @@ -788,17 +789,19 @@ module DSP48E1 ( if (CREG == 0) assign $C = C; else assign $C = 48'bx; + + assign $PCIN = PCIN; end else begin - assign $A = 30'bx, $B = 18'bx, $C = 48'bx, $D = 25'bx; + assign $A = 30'bx, $B = 18'bx, $C = 48'bx, $D = 25'bx, $PCIN = 48'bx; end if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") - $__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); + $__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") - $__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); + $__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") - $__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); + $__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); else $error("Invalid DSP48E1 configuration"); endgenerate diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index f83e97a2a..559439b85 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -113,10 +113,12 @@ module __NAME__ ( ($A *> P) = 2823; ($B *> P) = 2690; ($C *> P) = 1325; + ($PCIN *> P) = 1107; ($P *> P) = 0; ($A *> PCOUT) = 2970; ($B *> PCOUT) = 2838; ($C *> PCOUT) = 1474; + ($PCIN *> PCOUT) = 1255; ($PCOUT *> PCOUT) = 0; endspecify endmodule @@ -125,12 +127,14 @@ endmodule ($A *> P) = 3806; ($B *> P) = 2690; ($C *> P) = 1325; - ($D *> P) = 3700; + ($D *> P) = 3717; + ($PCIN *> P) = 1107; ($P *> P) = 0; ($A *> PCOUT) = 3954; ($B *> PCOUT) = 2838; ($C *> PCOUT) = 1474; ($D *> PCOUT) = 3700; + ($PCIN *> PCOUT) = 1255; ($PCOUT *> PCOUT) = 0; endspecify endmodule @@ -139,10 +143,12 @@ endmodule ($A *> P) = 1523; ($B *> P) = 1509; ($C *> P) = 1325; + ($PCIN *> P) = 1107; ($P *> P) = 0; ($A *> PCOUT) = 1671; ($B *> PCOUT) = 1658; ($C *> PCOUT) = 1474; + ($PCIN *> PCOUT) = 1255; ($PCOUT *> PCOUT) = 0; endspecify endmodule |