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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-21 15:45:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 6c34945371a0446159423b0d70f9f10dbc2c4d07 (patch) | |
| tree | 0f8cdc9be3d28a681eaee006442d6e65d9b92f79 /techlibs/xilinx | |
| parent | b65610fb628cfd38edcab3c64507477a58cbdd10 (diff) | |
| download | yosys-6c34945371a0446159423b0d70f9f10dbc2c4d07.tar.gz yosys-6c34945371a0446159423b0d70f9f10dbc2c4d07.tar.bz2 yosys-6c34945371a0446159423b0d70f9f10dbc2c4d07.zip | |
xilinx/ice40/ecp5: zinit requires selected wires, so select them all
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d05715ec2..d0de73f83 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -598,7 +598,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_ffs", "('-abc9' only)")) { if (abc9 || help_mode) { if (dff || help_mode) - run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "('-dff' only)"); + run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "('-dff' only)"); run("techmap -map " + ff_map_file); } } @@ -608,7 +608,7 @@ struct SynthXilinxPass : public ScriptPass if (flatten_before_abc) run("flatten"); if (help_mode) - run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for 'nowidelut', '-dff', '-retime')"); + run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')"); else if (abc9) { if (lut_size != 6) log_error("'synth_xilinx -abc9' not currently supported for LUT4-based devices.\n"); |