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* stat: Fix JSON output for empty designsJannis Harder2022-12-021-2/+2
* tee: Allow logging command output to a given scratchpad valueJannis Harder2022-12-023-0/+20
* Merge pull request #3567 from YosysHQ/tcl_fix_crashMiodrag Milanović2022-12-022-1/+8
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| * Fix tcl crash in case of error executing commandMiodrag Milanovic2022-11-302-1/+8
* | Bump versiongithub-actions[bot]2022-12-011-1/+1
* | Merge pull request #3551 from daglem/struct-array-swapped-rangeJannis Harder2022-12-013-21/+192
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| * Added asserts for current limitation of array dimensions in packed structsDag Lem2022-11-301-0/+8
| * Check for all cases of currently unsupported array dimensions in packed structsDag Lem2022-11-301-10/+13
| * Tests for unpacked arrays in packed structs are for the Yosys frontend onlyDag Lem2022-11-231-0/+4
| * Support for swapped ranges in second array dimensionDag Lem2022-11-232-3/+52
| * Support for arrays with swapped ranges within structsDag Lem2022-11-123-11/+118
* | Bump versiongithub-actions[bot]2022-11-291-1/+1
* | Merge pull request #3565 from jix/sat-def-formalJannis Harder2022-11-283-10/+46
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| * | sat: Add -set-def-formal option to force defined $any* outputsJannis Harder2022-11-283-10/+46
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* | Bump versiongithub-actions[bot]2022-11-261-1/+1
* | Merge pull request #3561 from YosysHQ/tcl_shellMiodrag Milanović2022-11-252-8/+34
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| * | Add TCL interactive shell modeMiodrag Milanovic2022-11-252-8/+34
* | | Merge pull request #3560 from YosysHQ/verific_confMiodrag Milanović2022-11-253-8/+43
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| * | update documentationMiodrag Milanovic2022-11-251-3/+3
| * | Support importing verilog configurations using VerificMiodrag Milanovic2022-11-253-5/+40
* | | Bump versiongithub-actions[bot]2022-11-251-1/+1
* | | Remove docs dependency on yosys repo (#3558)KrystalDelusion2022-11-2439-18/+905
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* | Merge pull request #3552 from daglem/fix-sv-c-array-dimensionsJannis Harder2022-11-231-3/+3
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| * | Correct interpretation of SystemVerilog C-style array dimensionsDag Lem2022-11-131-3/+3
* | | Bump versiongithub-actions[bot]2022-11-221-1/+1
* | | Merge branch 'zachjs-master'Jannis Harder2022-11-213-0/+52
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| * | | verilog: Support module-scoped task/function callsZachary Snow2022-10-293-0/+52
* | | | mention prerequisites in fsm_detect and fsm helpN. Engelhardt2022-11-212-0/+18
* | | | Bump versiongithub-actions[bot]2022-11-181-1/+1
* | | | fabulous: Allow adding extra custom prims and map rulesgatecat2022-11-174-0/+53
* | | | fabulous: improvements to the passgatecat2022-11-1713-139/+340
* | | | fabulous: Unify and update primitivesgatecat2022-11-173-852/+356
* | | | Introduce RegFile mappingsTaoBi222022-11-174-2/+95
* | | | Replace synth call with components, reintroduce flags and correct vpr flag im...TaoBi222022-11-171-4/+76
* | | | Reorder operations to load in primitive library before hierarchy passTaoBi222022-11-171-5/+6
* | | | Add plib flag to specify custom primitive library pathTaoBi222022-11-171-2/+14
* | | | Remove flattening from FABulous passTaoBi222022-11-171-11/+2
* | | | Remove ALL currently unused flags (some to be reintroduced later and passed t...TaoBi222022-11-171-82/+3
* | | | Add synth_fabulous ScriptPassTaoBi222022-11-178-0/+1282
* | | | Bump versiongithub-actions[bot]2022-11-171-1/+1
* | | | Slowing down clock to have same metadataMiodrag Milanovic2022-11-161-2/+2
* | | | Bump versiongithub-actions[bot]2022-11-161-1/+1
* | | | faketime to make PDFs uniqueMiodrag Milanovic2022-11-151-2/+2
* | | | Rst docs conversion (#3496)KrystalDelusion2022-11-1557-2/+7792
* | | | Merge pull request #3547 from YosysHQ/update_abcMiodrag Milanović2022-11-141-1/+1
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| * | | Update ABCMiodrag Milanovic2022-11-091-1/+1
* | | | Bump versiongithub-actions[bot]2022-11-101-1/+1
* | | | Add missing memory width assert preventing division by zero (#3546)Emil J2022-11-091-0/+1
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* | | Bump versiongithub-actions[bot]2022-11-091-1/+1
* | | Next dev cycleMiodrag Milanovic2022-11-082-2/+5
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