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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:33:04 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:33:04 -0800 |
| commit | 090e54569a58b26d616806337c28507d199ca43c (patch) | |
| tree | 04c1d6710288a2bd0b34d24e4c7d54114f2d630d /techlibs/xilinx | |
| parent | 0f4c1906bb82f03f77683b71e597ed4802fe316a (diff) | |
| download | yosys-090e54569a58b26d616806337c28507d199ca43c.tar.gz yosys-090e54569a58b26d616806337c28507d199ca43c.tar.bz2 yosys-090e54569a58b26d616806337c28507d199ca43c.zip | |
Remove RAMB{18,36}E1 from cells_xtra.py
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index ca301685b..749b1e0a7 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -163,8 +163,8 @@ CELLS = [ # Virtex 6 / Series 7. Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}), - Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}), + #Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}), + #Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}), # Ultrascale. Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), |