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xilinx
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Author
Age
Files
Lines
*
xilinx: Add tristate buffer mapping. (#1528)
Marcin Kościelnicki
2019-12-04
2
-9
/
+16
*
xilinx: Add models for LUTRAM cells. (#1537)
Marcin Kościelnicki
2019-12-04
3
-624
/
+831
*
xilinx: Add missing blackbox cell for BUFPLL.
Marcin Kościelnicki
2019-11-29
2
-0
/
+21
*
xilinx: Add simulation models for IOBUF and OBUFT.
Marcin Kościelnicki
2019-11-26
3
-25
/
+30
*
clkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki
2019-11-25
1
-1
/
+5
*
xilinx: Use INV instead of LUT1 when applicable
Marcin Kościelnicki
2019-11-25
1
-2
/
+6
*
xilinx: Add simulation models for MULT18X18* and DSP48A*.
Marcin Kościelnicki
2019-11-19
3
-132
/
+516
*
synth_xilinx: Merge blackbox primitive libraries.
Marcin Kościelnicki
2019-11-06
11
-23234
/
+29820
*
xilinx: Add URAM288 mapping for xcup
David Shah
2019-10-23
5
-2
/
+92
*
xilinx: Add support for UltraScale[+] BRAM mapping
David Shah
2019-10-23
7
-416
/
+1062
*
xilinx: Support multiplier mapping for all families.
Marcin Kościelnicki
2019-10-22
9
-9
/
+269
*
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
Clifford Wolf
2019-10-22
1
-0
/
+1
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*
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
N. Engelhardt
2019-10-17
1
-0
/
+1
*
|
Makefile: don't assume python is called `python3`
Sean Cross
2019-10-19
1
-1
/
+1
|
/
*
xilinx: Add simulation model for IBUFG.
Marcin Kościelnicki
2019-10-10
5
-33
/
+14
*
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
Eddie Hung
2019-10-08
11
-112
/
+121
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*
Merge branch 'master' into eddie/abc_to_abc9
Eddie Hung
2019-10-04
4
-181
/
+9
|
|
\
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*
|
Rename abc_* names/attributes to more precisely be abc9_*
Eddie Hung
2019-10-04
11
-111
/
+120
*
|
|
Add comment on why partial multipliers are 18x18
Eddie Hung
2019-10-04
1
-4
/
+8
*
|
|
Fix typo in check_label()
Eddie Hung
2019-10-04
1
-1
/
+1
|
|
/
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/
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*
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Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
Eddie Hung
2019-10-04
1
-2
/
+6
*
|
Remove DSP48E1 from *_cells_xtra.v
Eddie Hung
2019-10-04
3
-178
/
+2
|
/
*
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
Eddie Hung
2019-09-30
6
-122
/
+46
*
synth_xilinx: Support latches, remove used-up FF init values.
Marcin Kościelnicki
2019-09-30
2
-2
/
+76
*
Merge pull request #1359 from YosysHQ/xc7dsp
Eddie Hung
2019-09-29
11
-21
/
+3000
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*
Re-order
Eddie Hung
2019-09-27
1
-1
/
+1
|
*
Typo
Eddie Hung
2019-09-26
1
-1
/
+1
|
*
select once
Eddie Hung
2019-09-26
1
-3
/
+5
|
*
Stop trying to be too smart by prematurely optimising
Eddie Hung
2019-09-26
1
-1
/
+3
|
*
Call 'wreduce' after mul2dsp to avoid unextend()
Eddie Hung
2019-09-25
1
-0
/
+1
|
*
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
Eddie Hung
2019-09-25
1
-1
/
+1
|
*
Add (* techmap_autopurge *) to abc_unmap.v too
Eddie Hung
2019-09-23
1
-11
/
+11
|
*
Add techmap_autopurge to outputs in abc_map.v too
Eddie Hung
2019-09-23
1
-11
/
+11
|
*
Revert "Add a xilinx_finalise pass"
Eddie Hung
2019-09-23
3
-87
/
+0
|
*
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
Eddie Hung
2019-09-23
1
-38
/
+38
|
*
Revert "Vivado does not like zero width port connections"
Eddie Hung
2019-09-23
1
-2
/
+2
|
*
Vivado does not like zero width port connections
Eddie Hung
2019-09-23
1
-2
/
+2
|
*
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
Eddie Hung
2019-09-23
1
-38
/
+38
|
*
Add a xilinx_finalise pass
Eddie Hung
2019-09-23
3
-0
/
+87
|
*
Grammar
Eddie Hung
2019-09-20
1
-1
/
+1
|
*
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
Eddie Hung
2019-09-20
1
-1
/
+1
|
*
Tidy up, fix undriven
Eddie Hung
2019-09-19
1
-32
/
+34
|
*
$__ABC_REG to have WIDTH parameter
Eddie Hung
2019-09-19
2
-17
/
+18
|
*
Fix DSP48E1 timing by breaking P path if MREG or PREG
Eddie Hung
2019-09-19
4
-349
/
+363
|
*
Revert "Different approach to timing"
Eddie Hung
2019-09-19
4
-195
/
+405
|
*
Different approach to timing
Eddie Hung
2019-09-19
4
-405
/
+195
|
*
Suppress $anyseq warnings
Eddie Hung
2019-09-19
1
-15
/
+32
|
*
Use (* techmap_autopurge *) to suppress techmap warnings
Eddie Hung
2019-09-19
2
-94
/
+99
|
*
D is 25 bits not 24 bits wide
Eddie Hung
2019-09-19
1
-1
/
+1
|
*
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
Eddie Hung
2019-09-19
8
-90
/
+502
|
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