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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 10:33:16 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 10:33:16 -0700 |
commit | 93363c94a2e88e2cdbdb962ff9e10ba5dfe3f586 (patch) | |
tree | bd0fd95d0728b7b356fd20d9d546eb431701a26a /techlibs/xilinx | |
parent | b41d2fb4e49a5ee8cda1906405f32614b39302bc (diff) | |
download | yosys-93363c94a2e88e2cdbdb962ff9e10ba5dfe3f586.tar.gz yosys-93363c94a2e88e2cdbdb962ff9e10ba5dfe3f586.tar.bz2 yosys-93363c94a2e88e2cdbdb962ff9e10ba5dfe3f586.zip |
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
Diffstat (limited to 'techlibs/xilinx')
-rw-r--r-- | techlibs/xilinx/abc_model.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 0a8d531d7..f19235a27 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -102,7 +102,7 @@ endmodule (* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX ) `define ABC_DSP48E1(__NAME__) """ -module \$__ABC_DSP48E1_MULT ( +module __NAME__ ( output [29:0] ACOUT, output [17:0] BCOUT, output reg CARRYCASCOUT, |