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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 14:24:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 14:24:31 -0700 |
| commit | 4401e5f142d9728c09ac95e1cab9b30c449210fe (patch) | |
| tree | 6aee8773c341b197950dbfd7127161ebec745dd8 /techlibs/xilinx | |
| parent | 53817b85753deb3dc5647414de67de1373798049 (diff) | |
| download | yosys-4401e5f142d9728c09ac95e1cab9b30c449210fe.tar.gz yosys-4401e5f142d9728c09ac95e1cab9b30c449210fe.tar.bz2 yosys-4401e5f142d9728c09ac95e1cab9b30c449210fe.zip | |
Grammar
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc_model.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 1c69dd21c..0a8d531d7 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -47,7 +47,7 @@ endmodule // Modules used to model the comb/seq behaviour of DSP48E1 // With abc_map.v responsible for splicing the below modules -// into between the combinatorial DSP48E1 box (e.g. disconnecting +// between the combinatorial DSP48E1 box (e.g. disconnecting // A when AREG, MREG or PREG is enabled and splicing in the // "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below) // this acts to first disables the combinatorial path (as there |