| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 1 | -1/+5 | |
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| | * \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 1 | -0/+522 | |
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| | * | | | | | | | | | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 1 | -208/+16 | |
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| | * | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -47/+47 | |
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| | * | | | | | | | | | | | | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 | |
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| | * | | | | | | | | | | | | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 | |
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| | * | | | | | | | | | | | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 1 | -80/+80 | |
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| | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 1 | -0/+44 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -0/+463 | |
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| | * | | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTED | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 1 | -47/+247 | |
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| * | | | | | | | | | | | | | | | Fix DSP48E1 sim | Eddie Hung | 2020-01-06 | 1 | -3/+3 | |
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| * | | | | | | | | | | | | | | Wrap arrival functions inside `YOSYS too | Eddie Hung | 2020-01-06 | 1 | -0/+2 | |
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| * | | | | | | | | | | | | | | Fix return value of arrival time functions, fix word | Eddie Hung | 2020-01-06 | 1 | -18/+14 | |
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| * | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor | Eddie Hung | 2020-01-02 | 1 | -6/+6 | |
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| | * | | | | | | | | | | | | | ifdef __ICARUS__ -> ifndef YOSYS | Eddie Hung | 2020-01-01 | 1 | -6/+6 | |
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| * | | | | | | | | | | | | | | ifndef __ICARUS__ -> ifdef YOSYS | Eddie Hung | 2020-01-01 | 1 | -2/+2 | |
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| * | | | | | | | | | | | | | | Rework abc9's DSP48E1 model | Eddie Hung | 2020-01-01 | 1 | -0/+79 | |
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| * | | | | | | | | | | | / | Update timings for Xilinx S7 cells | Eddie Hung | 2019-12-30 | 1 | -15/+35 | |
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| * | | | | | | | | | | | | xilinx: Test our DSP48A/DSP48A1 simulation models. | Marcin Kościelnicki | 2019-12-23 | 1 | -3/+3 | |
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| * | | | | | | | | | | | Add abc9_arrival times for RAM{32,64}M | Eddie Hung | 2019-12-20 | 1 | -24/+10 | |
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| * | | | | | | | | | | xilinx: Add simulation models for remaining CLB primitives. | Marcin Kościelnicki | 2019-12-19 | 1 | -4/+197 | |
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| * | | | | | | | | | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 1 | -0/+35 | |
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| * | | | | | | | | | RAM64M8 to also have [5:0] for address | Eddie Hung | 2019-12-13 | 1 | -8/+8 | |
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| * | | | | | | | | | Fix RAM64M model to have 6 bit address bus | Eddie Hung | 2019-12-12 | 1 | -4/+4 | |
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| * | | | | | | | | xilinx: Add models for LUTRAM cells. (#1537) | Marcin Kościelnicki | 2019-12-04 | 1 | -0/+797 | |
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| * | | | | | | | xilinx: Add simulation models for IOBUF and OBUFT. | Marcin Kościelnicki | 2019-11-26 | 1 | -0/+28 | |
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| * | | | | | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -1/+5 | |
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| * | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*. | Marcin Kościelnicki | 2019-11-19 | 1 | -0/+511 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6) | |||||
| * | | | | | xilinx: Add simulation model for IBUFG. | Marcin Kościelnicki | 2019-10-10 | 1 | -0/+11 | |
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| * | | | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -19/+19 | |
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| * | | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 1 | -0/+44 | |
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| * | | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 1 | -8/+44 | |
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| | * | Use extractinv for synth_xilinx -ise | Marcin Kościelnicki | 2019-09-19 | 1 | -8/+44 | |
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| * | | Mis-spell | Eddie Hung | 2019-09-18 | 1 | -10/+25 | |
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| * | | Add pattern detection support for DSP48E1 model, check against vendor | Eddie Hung | 2019-09-18 | 1 | -4/+43 | |
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| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-05 | 1 | -26/+70 | |
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| | * | Remove trailing space | Eddie Hung | 2019-08-30 | 1 | -2/+2 | |
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| | * | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -15/+78 | |
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| | * | | Put attributes above port | Eddie Hung | 2019-08-23 | 1 | -19/+46 | |
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| | * | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 1 | -5/+10 | |
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| | * | | | Add abc_arrival to SRL* | Eddie Hung | 2019-08-21 | 1 | -3/+5 | |
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| | * | | | Oops | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| | * | | | xilinx to use abc_map.v with -max_iter 1 | Eddie Hung | 2019-08-20 | 1 | -3/+6 | |
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| | * | | | Add reference to FD* timing | Eddie Hung | 2019-08-20 | 1 | -0/+2 | |
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| | * | | | Remove sequential extension | Eddie Hung | 2019-08-20 | 1 | -8/+16 | |
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| | * | | | Remove SRL* delays from cells_sim.v | Eddie Hung | 2019-08-20 | 1 | -5/+3 | |
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| | * | | | Wrap LUTRAMs in order to capture comb/seq behaviour | Eddie Hung | 2019-08-20 | 1 | -15/+9 | |
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| | * | | | Add LUTRAM delays | Eddie Hung | 2019-08-20 | 1 | -3/+6 | |
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| | * | | | Use abc_{map,unmap,model}.v | Eddie Hung | 2019-08-20 | 1 | -8/+0 | |
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index : iCE40/yosys | |
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