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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-01 17:33:47 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-01 17:33:47 -0800 |
| commit | d0d3ab8f676cd355d74cb7b7f71fc5bfca0719a2 (patch) | |
| tree | fe20c47664b5c78b69f088ebd8a73b95948d69e5 /techlibs/xilinx/cells_sim.v | |
| parent | db04161eca76d4db7a01641429d2da6a3a8d3239 (diff) | |
| download | yosys-d0d3ab8f676cd355d74cb7b7f71fc5bfca0719a2.tar.gz yosys-d0d3ab8f676cd355d74cb7b7f71fc5bfca0719a2.tar.bz2 yosys-d0d3ab8f676cd355d74cb7b7f71fc5bfca0719a2.zip | |
ifndef __ICARUS__ -> ifdef YOSYS
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index d705451fe..2947fe692 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2160,13 +2160,13 @@ module DSP48E1 ( output reg [3:0] CARRYOUT, output reg MULTSIGNOUT, output OVERFLOW, -`ifndef __ICARUS__ +`ifdef YOSYS (* abc9_arrival = \DSP48E1.P_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) `endif output reg signed [47:0] P, output reg PATTERNBDETECT, output reg PATTERNDETECT, -`ifndef __ICARUS__ +`ifdef YOSYS (* abc9_arrival = \DSP48E1.PCOUT_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) `endif output [47:0] PCOUT, |