| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix files with CRLF line endings | Claire Xenia Wolf | 2021-06-09 | 1 | -31/+31 |
| * | synth_intel_alm: alternative synthesis for Intel FPGAs | Dan Ravensloft | 2020-04-15 | 1 | -0/+31 |
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index : iCE40/yosys | |
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