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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-11-19 10:19:00 +0000 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-15 11:40:41 +0200 |
| commit | 2e37e62e6b926ca1712b1636ef720748e382dc97 (patch) | |
| tree | 25936d690dff24f0cddcc5dbbfe68aea74500994 /techlibs/intel_alm/common/bram_m20k_map.v | |
| parent | 4c52691a58a469a525401bbc83c65f262b2a5504 (diff) | |
| download | yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.tar.gz yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.tar.bz2 yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.zip | |
synth_intel_alm: alternative synthesis for Intel FPGAs
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
Diffstat (limited to 'techlibs/intel_alm/common/bram_m20k_map.v')
| -rw-r--r-- | techlibs/intel_alm/common/bram_m20k_map.v | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/bram_m20k_map.v b/techlibs/intel_alm/common/bram_m20k_map.v new file mode 100644 index 000000000..92f41310f --- /dev/null +++ b/techlibs/intel_alm/common/bram_m20k_map.v @@ -0,0 +1,31 @@ +module __MISTRAL_M20K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+
+parameter CFG_ABITS = 10;
+parameter CFG_DBITS = 20;
+parameter CFG_ENABLE_A = 1;
+parameter CFG_ENABLE_B = 1;
+
+input CLK1;
+input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
+input [CFG_DBITS-1:0] A1DATA;
+output [CFG_DBITS-1:0] B1DATA;
+input [CFG_ENABLE_A-1:0] A1EN, B1EN;
+
+altsyncram #(
+ .operation_mode("dual_port"),
+ .ram_block_type("m20k"),
+ .widthad_a(CFG_ABITS),
+ .width_a(CFG_DBITS),
+ .widthad_b(CFG_ABITS),
+ .width_b(CFG_DBITS),
+) _TECHMAP_REPLACE_ (
+ .address_a(A1ADDR),
+ .data_a(A1DATA),
+ .wren_a(A1EN),
+ .address_b(B1ADDR),
+ .q_b(B1DATA),
+ .clock0(CLK1),
+ .clock1(CLK1)
+);
+
+endmodule
|