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* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-5/+8
* intel_alm: M10K write-enable is negative-trueLofty2022-03-096-7/+28
* intel_alm: disable 256x40 M10K modeLofty2021-12-221-9/+3
* intel_alm: preliminary Arria V supportLofty2021-11-256-7/+199
* CycloneV: Add (passthrough) support for cyclonev_oscillatorOlivier Galibert2021-10-171-1/+11
* CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_pu...Olivier Galibert2021-10-171-0/+8
* Fix files with CRLF line endingsClaire Xenia Wolf2021-06-091-31/+31
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-082-2/+2
* intel_alm: Fix illegal carry chainsgatecat2021-05-152-3/+5
* intel_alm: Add global buffer insertiongatecat2021-05-156-4/+78
* intel_alm: Add IO buffer insertiongatecat2021-05-156-7/+127
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
* intel_alm: better map wide but shallow multipliesDan Ravensloft2020-08-281-2/+6
* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-265-10/+103
* intel: move Cyclone V support to intel_almDan Ravensloft2020-08-203-1/+153
* intel_alm: fix typo in MISTRAL_MUL27X27 cell nameDan Ravensloft2020-08-131-1/+1
* intel_alm: add more megafunctions. NFC.Dan Ravensloft2020-08-121-0/+431
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+2
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-277-39/+127
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-1/+1
* intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-234-72/+91
* Revert "intel_alm: direct M10K instantiation"Lofty2020-07-137-122/+38
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-057-38/+122
* intel_alm: DSP inferenceDan Ravensloft2020-07-056-9/+186
* synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-042-121/+9
* Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-5/+4
* intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FFEddie Hung2020-07-042-47/+2
* intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLYEddie Hung2020-07-044-4/+4
* intel_alm: ABC9 sequential optimisationsDan Ravensloft2020-07-047-19/+149
* Use C++11 final/override keywords.whitequark2020-06-181-4/+4
* intel_alm: fix DFFE matchingDan Ravensloft2020-06-111-1/+1
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-0/+8
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+0
* intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-078-52/+143
* intel_alm: cleanup duplicationDan Ravensloft2020-04-245-113/+64
* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+10
* intel_alm: Documentation improvementsDan Ravensloft2020-04-213-14/+127
* synth_intel_alm: VQM supportDan Ravensloft2020-04-152-6/+3
* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1517-0/+1453
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 08:08:56 +0000