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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 10:25:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 8fbb55f4aba9ccb850680dc9c7ab582e8c964a4a (patch) | |
| tree | 33edc1fef5c872cb917086bcd6354501285c2258 /techlibs/intel_alm | |
| parent | 63246a5c0eb5780675384d00443e6e46b5e59603 (diff) | |
| download | yosys-8fbb55f4aba9ccb850680dc9c7ab582e8c964a4a.tar.gz yosys-8fbb55f4aba9ccb850680dc9c7ab582e8c964a4a.tar.bz2 yosys-8fbb55f4aba9ccb850680dc9c7ab582e8c964a4a.zip | |
synth_*: no need to explicitly read +/abc9_model.v
Diffstat (limited to 'techlibs/intel_alm')
| -rw-r--r-- | techlibs/intel_alm/synth_intel_alm.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index bf9e746b8..0f844961e 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -209,7 +209,6 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("map_luts")) { - run("read_verilog -icells -specify -lib +/abc9_model.v"); run("abc9 -maxlut 6 -W 200"); run("techmap -map +/intel_alm/common/alm_map.v"); run("opt -fast"); |