iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge remote-tracking branch 'origin/master' into xaig_arrival	Eddie Hung	2019-08-30	3	-3/+3
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\| *	Rename boxes too	Eddie Hung	2019-08-29	3	-3/+3
\| *	Do not overwrite LUT param	Eddie Hung	2019-08-28	1	-1/+0
* \|	Comment out SB_MAC16 arrival time for now, need to handle all its modes	Eddie Hung	2019-08-28	1	-1/+1
* \|	Add arrival for SB_MAC16.O	Eddie Hung	2019-08-28	1	-0/+1
* \|	Add arrival times for U	Eddie Hung	2019-08-28	1	-0/+26
* \|	LX -> LP	Eddie Hung	2019-08-28	1	-1/+1
* \|	Round not floor	Eddie Hung	2019-08-28	1	-21/+21
* \|	Add LP timings	Eddie Hung	2019-08-28	1	-0/+26
* \|	LX -> LP	Eddie Hung	2019-08-28	1	-1/+1
* \|	Do not overwrite LUT param	Eddie Hung	2019-08-28	1	-1/+0
* \|	Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival	Eddie Hung	2019-08-28	2	-1/+48
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\| *	Trailing comma	Eddie Hung	2019-08-28	1	-1/+1
\| *	Adapt to $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-08-28	1	-3/+5
\| *	Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"	Eddie Hung	2019-08-28	1	-0/+45
* \|	Add arrival times for HX devices	Eddie Hung	2019-08-28	1	-21/+114
* \|	Specify ice40 family to cells_sim.v using define	Eddie Hung	2019-08-28	1	-1/+8
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*	Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with	Eddie Hung	2019-08-28	1	-45/+0
*	Update box size and timings	Eddie Hung	2019-08-28	3	-12/+12
*	Update to new $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-08-28	1	-11/+8
*	Put abc_* attributes above port	Eddie Hung	2019-08-23	1	-2/+4
*	Merge pull request #1304 from YosysHQ/eddie/abc9_refactor	Eddie Hung	2019-08-20	1	-2/+8
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\| *	Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro	Eddie Hung	2019-08-19	1	-2/+2
\| *	Update abc_* attr in ecp5 and ice40	Eddie Hung	2019-08-16	1	-2/+8
* \|	Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-08-12	1	-1/+1
* \|	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...	Eddie Hung	2019-08-12	6	-150/+32
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*	Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"	David Shah	2019-08-10	6	-32/+150
*	Merge pull request #1258 from YosysHQ/eddie/cleanup	Clifford Wolf	2019-08-10	3	-5/+5
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\| *	substr() -> compare()	Eddie Hung	2019-08-07	1	-3/+3
\| *	RTLIL::S{0,1} -> State::S{0,1}	Eddie Hung	2019-08-07	1	-1/+1
\| *	stoi -> atoi	Eddie Hung	2019-08-07	1	-1/+1
* \|	Allow whitebox modules to be overwritten	Eddie Hung	2019-08-07	1	-2/+0
* \|	Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER	Eddie Hung	2019-08-07	3	-10/+17
* \|	Add test	Eddie Hung	2019-08-07	1	-1/+10
* \|	Remove ice40_unlut	Eddie Hung	2019-08-07	2	-107/+0
* \|	Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER	Eddie Hung	2019-08-07	3	-39/+14
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*	ice40: Fix test_dsp_model.sh	David Shah	2019-07-19	1	-1/+1
*	ice40/cells_sim.v: Fix sign of J and K partial products	David Shah	2019-07-19	1	-5/+7
*	ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode	David Shah	2019-07-19	1	-2/+2
*	Add tests for all combinations of A and B signedness for comb mul	Eddie Hung	2019-07-19	2	-1/+229
*	Don't copy ref if exists already	Eddie Hung	2019-07-19	1	-1/+3
*	Merge pull request #1184 from whitequark/synth-better-labels	Clifford Wolf	2019-07-18	1	-2/+2
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\| *	synth_{ice40,ecp5}: more sensible pass label naming.	whitequark	2019-07-16	1	-2/+2
* \|	ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map	Sylvain Munaut	2019-07-16	2	-4/+4
* \|	Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix	Eddie Hung	2019-07-16	8	-29/+120
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\| *	$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark	Eddie Hung	2019-07-15	7	-8/+8
\| *	ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT	Eddie Hung	2019-07-13	1	-9/+7
\| *	Use Const::from_string() not its constructor...	Eddie Hung	2019-07-12	1	-1/+1
\| *	Off by one	Eddie Hung	2019-07-12	1	-1/+1
\| *	Fix spacing	Eddie Hung	2019-07-12	1	-1/+1