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| author | Sylvain Munaut <tnt@246tNt.com> | 2019-07-16 23:57:15 +0200 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2019-07-16 23:57:15 +0200 |
| commit | f28e38de9994151ea4e22608441dbc9e116d7b8c (patch) | |
| tree | a83315c169a7802f93e5021ef3cb51595ac64aa3 /techlibs/ice40 | |
| parent | 5939b5d636f80d4f9345f5b8d0247332d533b68c (diff) | |
| download | yosys-f28e38de9994151ea4e22608441dbc9e116d7b8c.tar.gz yosys-f28e38de9994151ea4e22608441dbc9e116d7b8c.tar.bz2 yosys-f28e38de9994151ea4e22608441dbc9e116d7b8c.zip | |
ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d
needed matching adaptation when converting and optimizing LUTs during
the relut process
Fixes #1187
(Diagnosis of the issue by @daveshah1 on IRC)
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/ice40_unlut.cc | 6 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc index d16e6e6a3..f3f70ac1f 100644 --- a/techlibs/ice40/ice40_unlut.cc +++ b/techlibs/ice40/ice40_unlut.cc @@ -56,10 +56,10 @@ static void run_ice40_unlut(Module *module) cell->unsetParam("\\LUT_INIT"); cell->setPort("\\A", SigSpec({ - get_bit_or_zero(cell->getPort("\\I3")), - get_bit_or_zero(cell->getPort("\\I2")), + get_bit_or_zero(cell->getPort("\\I0")), get_bit_or_zero(cell->getPort("\\I1")), - get_bit_or_zero(cell->getPort("\\I0")) + get_bit_or_zero(cell->getPort("\\I2")), + get_bit_or_zero(cell->getPort("\\I3")) })); cell->setPort("\\Y", cell->getPort("\\O")[0]); cell->unsetPort("\\I0"); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index b3d30791a..78ac5ea13 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -345,7 +345,7 @@ struct SynthIce40Pass : public ScriptPass } run("clean"); run("ice40_unlut"); - run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3"); + run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0"); } if (check_label("map_cells")) |