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| * | Add synth -keepdc optionEddie Hung2019-07-081-2/+13
* | | mul2dsp to create cells that can be interchanged with $mulEddie Hung2019-07-181-1/+7
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* | Make consistentEddie Hung2019-07-181-1/+2
* | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
* | Working for unsignedEddie Hung2019-07-181-52/+28
* | CleanupEddie Hung2019-07-181-70/+58
* | mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
* | Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
* | A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
* | Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
* | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-161-22/+26
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| * | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
| * | mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
* | | Do not swap if equalsEddie Hung2019-07-151-1/+1
* | | OUT port to Y in generic DSPEddie Hung2019-07-151-1/+1
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* | Only swap if B_WIDTH > A_WIDTHEddie Hung2019-07-151-1/+1
* | Tidy upEddie Hung2019-07-151-39/+26
* | mul2dsp: Fix typoDavid Shah2019-07-081-1/+1
* | Add mul2dsp multiplier splitting rule and ECP5 mappingDavid Shah2019-07-082-0/+238
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* Make doc consistentEddie Hung2019-06-141-1/+4
* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-123-2/+182
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| * Add "wreduce -keepdc", fixes #1016Clifford Wolf2019-05-201-2/+4
| * Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-0/+2
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| | * Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-301-0/+2
| * | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| * | Improve $specrule interfaceClifford Wolf2019-04-231-3/+4
| * | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+28
| * | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...Clifford Wolf2019-04-231-70/+70
| * | Add $specify2 and $specify3 cells to simlibClifford Wolf2019-04-231-0/+147
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* / synth to take -abc9 argumentEddie Hung2019-02-201-5/+13
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* Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-021-6/+40
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| * synth: add k-LUT mode.whitequark2019-01-021-2/+36
| * synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
* | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-022-1/+106
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| * cmp2lut: new techmap pass.whitequark2019-01-022-1/+106
* | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-022-2/+2
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* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-052-0/+88
* Fix typo.whitequark2018-12-051-2/+2
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-202-8/+8
* Make -nordff the default in "prep"Clifford Wolf2018-05-301-9/+13
* Add "synth -noshare"Clifford Wolf2018-03-041-2/+11
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-0/+24
* Fix minor typo in "prep" help messageClifford Wolf2017-12-191-1/+1
* Add dff2ff.v techmap fileClifford Wolf2017-05-312-0/+15
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-0/+38
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-0/+16
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+8
* Added $anyseq cell typeClifford Wolf2016-10-141-0/+12
* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-142-2/+23
* Added $ff and $_FF_ cell typesClifford Wolf2016-10-122-1/+14