diff options
| author | Clifford Wolf <clifford@clifford.at> | 2017-02-25 10:36:39 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-25 10:36:39 +0100 |
| commit | 5f1d0b1024981b6ede2988bf8c5812b37c87d0e9 (patch) | |
| tree | 75e48829241c9c65b5c9c7a34cc21048285ea48b /techlibs/common | |
| parent | 7af9727f78263d2fc41178396791f51a680acdfa (diff) | |
| download | yosys-5f1d0b1024981b6ede2988bf8c5812b37c87d0e9.tar.gz yosys-5f1d0b1024981b6ede2988bf8c5812b37c87d0e9.tar.bz2 yosys-5f1d0b1024981b6ede2988bf8c5812b37c87d0e9.zip | |
Add $live and $fair cell types, add support for s_eventually keyword
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/simlib.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index d0abd3b34..276503fe8 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1305,6 +1305,22 @@ endmodule // -------------------------------------------------------- +module \$live (A, EN); + +input A, EN; + +endmodule + +// -------------------------------------------------------- + +module \$fair (A, EN); + +input A, EN; + +endmodule + +// -------------------------------------------------------- + module \$cover (A, EN); input A, EN; |