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author | Clifford Wolf <clifford@clifford.at> | 2016-10-12 01:18:39 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-10-12 01:18:39 +0200 |
commit | 8ebba8a35f0a5dbf3a044ab84575edfc46c99d77 (patch) | |
tree | 180fce8de63b6908d00ccefb59a6f9a3a930b5a4 /techlibs/common | |
parent | 4a981a3bd81836cd15059db56f01b60b11068742 (diff) | |
download | yosys-8ebba8a35f0a5dbf3a044ab84575edfc46c99d77.tar.gz yosys-8ebba8a35f0a5dbf3a044ab84575edfc46c99d77.tar.bz2 yosys-8ebba8a35f0a5dbf3a044ab84575edfc46c99d77.zip |
Added $ff and $_FF_ cell types
Diffstat (limited to 'techlibs/common')
-rw-r--r-- | techlibs/common/simlib.v | 13 | ||||
-rw-r--r-- | techlibs/common/techmap.v | 2 |
2 files changed, 14 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 922a47cab..db818269b 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1383,6 +1383,19 @@ endmodule `endif // -------------------------------------------------------- +module \$ff (D, Q); + +parameter WIDTH = 0; + +input [WIDTH-1:0] D; +output [WIDTH-1:0] Q; + +assign D = Q; + +endmodule + +// -------------------------------------------------------- + module \$dff (CLK, D, Q); parameter WIDTH = 0; diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 90c4ed7eb..d7ec3947e 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -64,7 +64,7 @@ module _90_simplemap_various; endmodule (* techmap_simplemap *) -(* techmap_celltype = "$sr $dff $dffe $adff $dffsr $dlatch" *) +(* techmap_celltype = "$sr $ff $dff $dffe $adff $dffsr $dlatch" *) module _90_simplemap_registers; endmodule |