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* anlogic: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-189-303/+585
* Removed dbits 8 since 9 will always be pickedMiodrag Milanovic2022-01-191-2/+0
* anlogic: support BRAM mappingIcenowy Zheng2021-12-176-1/+269
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-084-6/+6
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
* anlogic: Fix FF mapping.Marcelina Kościelnicka2020-07-171-12/+12
* anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-143-50/+35
* Use C++11 final/override keywords.whitequark2020-06-183-8/+8
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-0/+10
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-022-31/+31
* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
* Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-025-10/+22
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| * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-015-10/+22
* | Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-021-2/+2
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| * | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
| * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
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* / Fix anlogic async flop mappingEddie Hung2020-01-011-8/+8
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* make note that it is for latch modeMiodrag Milanovic2019-09-181-0/+1
* better lut handlingMiodrag Milanovic2019-09-181-4/+14
* Added simulation models for Efinix and AnlogicMiodrag Milanovic2019-09-151-1/+79
* Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
* Proper arith for Anlogic and use standard passMiodrag Milanovic2019-08-125-91/+162
* anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
* Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-012-4/+4
* Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-281-2/+2
* Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
* Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
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| * anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
* | Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-022-14/+15
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| * | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
* | | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* | | anlogic: add latch cellsIcenowy Zheng2018-12-251-0/+12
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* | Merge pull request #752 from Icenowy/anlogic-lut-costClifford Wolf2018-12-191-1/+1
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| * | Anlogic: let LUT5/6 have more cost than LUT4-Icenowy Zheng2018-12-191-1/+1
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* | Merge pull request #753 from Icenowy/anlogic-makefile-fixClifford Wolf2018-12-191-0/+1
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| * | anlogic: fix Makefile.incIcenowy Zheng2018-12-191-0/+1
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* / anlogic: fix dbits of Anlogic Eagle DRAM16X4Icenowy Zheng2018-12-181-1/+1
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* anlogic: add support for Eagle Distributed RAMIcenowy Zheng2018-12-174-1/+43
* Revert "Leave only real black box cells"Icenowy Zheng2018-12-171-0/+312
* Leave only real black box cellsMiodrag Milanovic2018-12-021-312/+0
* Initial support for Anlogic FPGAMiodrag Milanovic2018-12-017-0/+1590
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