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| author | Icenowy Zheng <icenowy@aosc.io> | 2018-12-25 22:47:46 +0800 |
|---|---|---|
| committer | Icenowy Zheng <icenowy@aosc.io> | 2018-12-25 22:47:46 +0800 |
| commit | 1b369442995ea3f83d0d0445bb34c8f8115c10a3 (patch) | |
| tree | 49d7c8584cdc50641ac9f4ddcd4b7fec87e4eb7f /techlibs/anlogic | |
| parent | 93d44bb9a613b46a80642b8ce71295db18fadbc5 (diff) | |
| download | yosys-1b369442995ea3f83d0d0445bb34c8f8115c10a3.tar.gz yosys-1b369442995ea3f83d0d0445bb34c8f8115c10a3.tar.bz2 yosys-1b369442995ea3f83d0d0445bb34c8f8115c10a3.zip | |
anlogic: add latch cells
Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Diffstat (limited to 'techlibs/anlogic')
| -rw-r--r-- | techlibs/anlogic/cells_map.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v index 36b920ef0..f54a81dcc 100644 --- a/techlibs/anlogic/cells_map.v +++ b/techlibs/anlogic/cells_map.v @@ -15,6 +15,18 @@ module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REG module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule + `ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; |