| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Test fixes for latest iverilog | Miodrag Milanovic | 2022-09-21 | 1 | -2/+1 |
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 3 | -3/+3 |
| * | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 2 | -0/+7 |
| * | Remove executable flag from files | Miodrag Milanovic | 2020-02-15 | 3 | -0/+0 |
| * | Reduce amount of trailing whitespace in code base | Larry Doolittle | 2019-02-28 | 1 | -3/+3 |
| * | Fix cells_sim.v for Achronix FPGA | Miodrag Milanovic | 2019-01-04 | 1 | -1/+1 |
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -8/+8 |
| * | Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val... | c60k28 | 2018-03-31 | 2 | -107/+44 |
| * | Squelch trailing whitespace, including meta-whitespace | Larry Doolittle | 2018-03-11 | 2 | -5/+5 |
| * | Organizing Speedster file names | dh73 | 2017-11-08 | 3 | -0/+0 |
| * | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ... | dh73 | 2017-10-01 | 3 | -0/+280 |
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index : iCE40/yosys | |
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