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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-09-21 15:46:43 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-09-21 15:46:43 +0200 |
| commit | 1ecf6aee9b331efebeca1bd95a3d5125abf8da50 (patch) | |
| tree | 279f98b936b6c739dce2cd0371de6307f3637550 /techlibs/achronix/speedster22i | |
| parent | a217450524e21222d8d32bd448f1ea2291685258 (diff) | |
| download | yosys-1ecf6aee9b331efebeca1bd95a3d5125abf8da50.tar.gz yosys-1ecf6aee9b331efebeca1bd95a3d5125abf8da50.tar.bz2 yosys-1ecf6aee9b331efebeca1bd95a3d5125abf8da50.zip | |
Test fixes for latest iverilog
Diffstat (limited to 'techlibs/achronix/speedster22i')
| -rw-r--r-- | techlibs/achronix/speedster22i/cells_sim.v | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v index 6c87adb94..fc15e0966 100644 --- a/techlibs/achronix/speedster22i/cells_sim.v +++ b/techlibs/achronix/speedster22i/cells_sim.v @@ -68,9 +68,8 @@ end assign dout = combout_rt & 1'b1; endmodule -module DFF (output q, +module DFF (output reg q, input d, ck); - reg q; always @(posedge ck) q <= d; |