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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2019-02-26 10:28:42 -0800 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-28 14:58:11 -0800 |
| commit | e2fc18f27b5e9f506724a486787c2106b9f7fb4f (patch) | |
| tree | efab7457784570035c54d67045292f6cda2f1447 /techlibs/achronix/speedster22i | |
| parent | 68a693717347cefc057cbf1a1c8d0f66500dec4f (diff) | |
| download | yosys-e2fc18f27b5e9f506724a486787c2106b9f7fb4f.tar.gz yosys-e2fc18f27b5e9f506724a486787c2106b9f7fb4f.tar.bz2 yosys-e2fc18f27b5e9f506724a486787c2106b9f7fb4f.zip | |
Reduce amount of trailing whitespace in code base
Diffstat (limited to 'techlibs/achronix/speedster22i')
| -rwxr-xr-x | techlibs/achronix/speedster22i/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v index a94dce9b1..a0c60b4be 100755 --- a/techlibs/achronix/speedster22i/cells_sim.v +++ b/techlibs/achronix/speedster22i/cells_sim.v @@ -30,7 +30,7 @@ endmodule module PADOUT (output padout, input padin, input oe); assign padout = padin; assign oe = oe; -endmodule +endmodule module LUT4 (output dout, input din0, din1, din2, din3); @@ -66,14 +66,14 @@ always @(dataa_w or datab_w or datac_w or datad_w) begin datac_w, datad_w); end assign dout = combout_rt & 1'b1; -endmodule +endmodule module DFF (output q, input d, ck); reg q; always @(posedge ck) q <= d; - + endmodule |