| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-18 | 5 | -106/+179 |
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| | * | Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters | Eddie Hung | 2019-07-16 | 1 | -44/+127 |
| | |\ | | | | | | | abc9: push inverters driving box inputs (comb outputs) through $lut soft logic | ||||
| | | * | Add comment | Eddie Hung | 2019-07-13 | 1 | -0/+5 |
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| | | * | duplicate -> clone | Eddie Hung | 2019-07-12 | 1 | -3/+3 |
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| | | * | More cleanup | Eddie Hung | 2019-07-12 | 1 | -8/+2 |
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| | | * | Cleanup | Eddie Hung | 2019-07-12 | 1 | -29/+51 |
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| | | * | Cleanup | Eddie Hung | 2019-07-12 | 1 | -10/+4 |
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| | | * | Cleanup | Eddie Hung | 2019-07-12 | 1 | -15/+24 |
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| | | * | More cleanup | Eddie Hung | 2019-07-12 | 1 | -11/+10 |
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| | | * | Cleanup | Eddie Hung | 2019-07-12 | 1 | -46/+16 |
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| | | * | Cleanup | Eddie Hung | 2019-07-12 | 1 | -7/+1 |
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| | | * | Cleanup | Eddie Hung | 2019-07-12 | 1 | -13/+109 |
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| | * | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix | Eddie Hung | 2019-07-16 | 1 | -2/+2 |
| | |\ \ | | | | | | | | | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box | ||||
| | | * | | Do not double count cells in abc | Eddie Hung | 2019-07-12 | 1 | -2/+2 |
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| | * | | Fix check logic in extract_fa | Miodrag Milanovic | 2019-07-16 | 1 | -2/+2 |
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| | * | | Merge pull request #1189 from YosysHQ/eddie/fix1151 | Clifford Wolf | 2019-07-15 | 1 | -0/+4 |
| | |\ \ | | | | | | | | | Error out if enable > dbits in memory_bram file | ||||
| | | * | | Error out if enable > dbits | Eddie Hung | 2019-07-13 | 1 | -0/+4 |
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| | * | | Merge pull request #1190 from YosysHQ/eddie/fix_1099 | Clifford Wolf | 2019-07-15 | 1 | -4/+8 |
| | |\ \ | | | | | | | | | extract_fa to return nothing more gracefully | ||||
| | | * | | If ConstEval fails do not log_abort() but return gracefully | Eddie Hung | 2019-07-13 | 1 | -4/+8 |
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| | * / | opt_lut: make less chatty. | whitequark | 2019-07-13 | 1 | -56/+38 |
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| * | | Check if RHS is empty first | Eddie Hung | 2019-07-18 | 1 | -0/+2 |
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| * | | Do not autoremove ffP aor muxP | Eddie Hung | 2019-07-18 | 1 | -2/+0 |
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| * | | Improve pattern matcher to match subsets of $dffe? cells | Eddie Hung | 2019-07-18 | 2 | -12/+22 |
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| * | | Improve A/B reg packing | Eddie Hung | 2019-07-18 | 2 | -6/+11 |
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| * | | Do not autoremove A/B registers since they might have other consumers | Eddie Hung | 2019-07-18 | 1 | -2/+0 |
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| * | | Fix xilinx_dsp index cast | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
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| * | | Wrong wildcard symbol | Eddie Hung | 2019-07-18 | 1 | -1/+1 |
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| * | | Pattern matcher to check pool of bits, not exactly | Eddie Hung | 2019-07-17 | 2 | -5/+11 |
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| * | | Signed extension | Eddie Hung | 2019-07-16 | 2 | -6/+6 |
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| * | | Add support {A,B,P}REG packing | Eddie Hung | 2019-07-16 | 2 | -55/+94 |
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| * | | Oops forgot these files | Eddie Hung | 2019-07-15 | 1 | -2/+7 |
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| * | | Add xilinx_dsp for register packing | Eddie Hung | 2019-07-15 | 3 | -2/+192 |
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| * | Enable &mfs for abc9, even if it only currently works for ice40 | Eddie Hung | 2019-07-11 | 1 | -1/+1 |
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| * | Merge pull request #1179 from whitequark/attrmap-proc | Clifford Wolf | 2019-07-11 | 1 | -0/+19 |
| |\ | | | | | attrmap: also consider process, switch and case attributes | ||||
| | * | attrmap: also consider process, switch and case attributes. | whitequark | 2019-07-10 | 1 | -0/+19 |
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| * | | Merge pull request #1177 from YosysHQ/clifford/async | Clifford Wolf | 2019-07-10 | 1 | -0/+7 |
| |\ \ | |/ |/| | Fix clk2fflogic adff reset semantic to negative hold time on reset | ||||
| | * | Fix tests/various/async FFL test | Clifford Wolf | 2019-07-09 | 1 | -0/+7 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #1174 from YosysHQ/eddie/fix1173 | Clifford Wolf | 2019-07-09 | 1 | -0/+3 |
| |\ \ | | | | | | | Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero | ||||
| | * | | Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero | Eddie Hung | 2019-07-09 | 1 | -0/+3 |
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| * / | Revert "Add "synth -keepdc" option" | Eddie Hung | 2019-07-09 | 1 | -1/+1 |
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| * | Merge pull request #1168 from whitequark/bugpoint-processes | Clifford Wolf | 2019-07-09 | 2 | -17/+105 |
| |\ | | | | | Add support for processes in bugpoint | ||||
| | * | bugpoint: add -assigns and -updates options. | whitequark | 2019-07-09 | 1 | -9/+81 |
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| | * | proc_clean: add -quiet option. | whitequark | 2019-07-09 | 1 | -8/+24 |
| | | | | | | | | | This is useful for other passes that call it often, like bugpoint. | ||||
| * | | Merge pull request #1169 from whitequark/more-proc-cleanups | Clifford Wolf | 2019-07-09 | 5 | -22/+168 |
| |\ \ | | | | | | | A new proc_prune pass | ||||
| | * | | proc_prune: promote assigns to module connections when legal. | whitequark | 2019-07-09 | 3 | -33/+42 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This can pave the way for further transformations by exposing identities that were previously hidden in a process to any pass that uses SigMap. Indeed, this commit removes some ad-hoc logic from proc_init that appears to have been tailored to the output of genrtlil in favor of using `SigMap.apply()`. (This removal is not optional, as the ad-hoc logic cannot cope with the result of running proc_prune; a similar issue was fixed in proc_arst.) | ||||
| | * | | proc_prune: new pass. | whitequark | 2019-07-09 | 3 | -1/+138 |
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The proc_prune pass is similar in nature to proc_rmdead pass: while proc_rmdead removes branches that never become active because another branch preempts it, proc_prune removes assignments that never become active because another assignment preempts them. Genrtlil contains logic similar to the proc_prune pass, but their purpose is different: genrtlil has to prune assignments to adapt the semantics of blocking assignments in HDLs (latest assignment wins) to semantics of assignments in RTLIL processes (assignment in the most specific case wins). On the other hand proc_prune is a general purpose RTLIL simplification that benefits all frontends, even those not using the Yosys AST library. The proc_prune pass is added to the proc script after proc_rmdead, since it gives better results with fewer branches. | ||||
| * | | Merge pull request #1163 from whitequark/more-case-attrs | Clifford Wolf | 2019-07-09 | 1 | -10/+16 |
| |\ \ | | | | | | | More support for case rule attributes | ||||
| | * | | proc_mux: consider \src attribute on CaseRule. | whitequark | 2019-07-08 | 1 | -10/+16 |
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| * | | Clarify 'wreduce -keepdc' doc | Eddie Hung | 2019-07-08 | 1 | -1/+1 |
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| * | | Update muxcover doc as per @ZirconiumX | Eddie Hung | 2019-07-08 | 1 | -5/+10 |
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index : iCE40/yosys | |
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