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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:22:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:22:00 -0700 |
| commit | 802470746c320676d61431d420e33d34c239da84 (patch) | |
| tree | a9ee99f3af332cccb9043d60d8489a5f768dae80 /passes | |
| parent | e22a7522422ec5f2f6db52d4e9c98d09868ea3e3 (diff) | |
| download | yosys-802470746c320676d61431d420e33d34c239da84.tar.gz yosys-802470746c320676d61431d420e33d34c239da84.tar.bz2 yosys-802470746c320676d61431d420e33d34c239da84.zip | |
Check if RHS is empty first
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index c2bec4c54..7a175123e 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -11,6 +11,7 @@ match ffA select ffA->type.in($dff, $dffe) // DSP48E1 does not support clock inversion select param(ffA, \CLK_POLARITY).as_bool() + filter !port(dsp, \A).remove_const().empty() filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set()) optional endmatch @@ -24,6 +25,7 @@ match ffB select ffB->type.in($dff, $dffe) // DSP48E1 does not support clock inversion select param(ffB, \CLK_POLARITY).as_bool() + filter !port(dsp, \B).remove_const().empty() filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set()) optional endmatch |