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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-09 22:44:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-07-09 22:44:39 +0200 |
| commit | 9546ccdbd348b1dc056884a536246801cdf1c4f1 (patch) | |
| tree | 1a28b466090a49b71806ed2fa7f428f6cf3c2fe3 /passes | |
| parent | 513862148211401fe71fb7966c81773042665acd (diff) | |
| download | yosys-9546ccdbd348b1dc056884a536246801cdf1c4f1.tar.gz yosys-9546ccdbd348b1dc056884a536246801cdf1c4f1.tar.bz2 yosys-9546ccdbd348b1dc056884a536246801cdf1c4f1.zip | |
Fix tests/various/async FFL test
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 49ec795d3..4bb4aa047 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -253,6 +253,13 @@ struct Clk2fflogicPass : public Pass { SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge); Const rstval = cell->parameters["\\ARST_VALUE"]; + Wire *past_arst = module->addWire(NEW_ID); + module->addFf(NEW_ID, arst, past_arst); + if (cell->parameters["\\ARST_POLARITY"].as_bool()) + arst = module->LogicOr(NEW_ID, arst, past_arst); + else + arst = module->LogicAnd(NEW_ID, arst, past_arst); + if (cell->parameters["\\ARST_POLARITY"].as_bool()) module->addMux(NEW_ID, qval, rstval, arst, sig_q); else |