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authorClifford Wolf <clifford@clifford.at>2019-07-11 07:23:28 +0200
committerGitHub <noreply@github.com>2019-07-11 07:23:28 +0200
commitfd3d5cefad89a396c9807bf3b8dc7349c1a765f1 (patch)
tree3949a915bb2a9d3a0c06f77460a2a97518f07563 /passes
parentbb2144ae733f1a2c5e629a8251bfbdcc15559aa4 (diff)
parentea447220dab2a5a66adb3a78ca2789068f046f3a (diff)
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Merge pull request #1179 from whitequark/attrmap-proc
attrmap: also consider process, switch and case attributes
Diffstat (limited to 'passes')
-rw-r--r--passes/techmap/attrmap.cc19
1 files changed, 19 insertions, 0 deletions
diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
index aa48e1125..a38638e0b 100644
--- a/passes/techmap/attrmap.cc
+++ b/passes/techmap/attrmap.cc
@@ -263,6 +263,25 @@ struct AttrmapPass : public Pass {
for (auto cell : module->selected_cells())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->attributes);
+
+ for (auto proc : module->processes)
+ {
+ if (!design->selected(module, proc.second))
+ continue;
+ attrmap_apply(stringf("%s.%s", log_id(module), log_id(proc.first)), actions, proc.second->attributes);
+
+ std::vector<RTLIL::CaseRule*> all_cases = {&proc.second->root_case};
+ while (!all_cases.empty()) {
+ RTLIL::CaseRule *cs = all_cases.back();
+ all_cases.pop_back();
+ attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc.first)), actions, cs->attributes);
+
+ for (auto &sw : cs->switches) {
+ attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc.first)), actions, sw->attributes);
+ all_cases.insert(all_cases.end(), sw->cases.begin(), sw->cases.end());
+ }
+ }
+ }
}
}
}