diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-13 00:52:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-13 00:52:21 -0700 |
| commit | fb062c3426e8acb5b3f54dfed7209631208fec81 (patch) | |
| tree | 7ae0f199b98b7e4566f7d40f8b60418b9b104994 /passes | |
| parent | 41243a53b384a9ecfadd7b424c9e22c7c84fb721 (diff) | |
| download | yosys-fb062c3426e8acb5b3f54dfed7209631208fec81.tar.gz yosys-fb062c3426e8acb5b3f54dfed7209631208fec81.tar.bz2 yosys-fb062c3426e8acb5b3f54dfed7209631208fec81.zip | |
Add comment
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 4a6ec3a47..658bb1225 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -787,6 +787,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri sink_cell->setParam("\\LUT", mask); } + // Since we have rewritten all sinks (which we know + // to be only LUTs) to be after the inverter, we can + // go ahead and clone the LUT with the expectation + // that the original driving LUT will become dangling + // and get cleaned away clone_lut: driver_mask = driver_lut->getParam("\\LUT"); for (auto &b : driver_mask.bits) { |