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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 15:31:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 19:30:18 -0700 |
| commit | 399e1ec87033d44d8d9e55b6a15a06e4412eb81a (patch) | |
| tree | bebfc1a31037261c00ea61ddc5477820821825a7 /passes | |
| parent | 58dbb28fd3e1176d9f8a1355897cf4b56b7b46b2 (diff) | |
| download | yosys-399e1ec87033d44d8d9e55b6a15a06e4412eb81a.tar.gz yosys-399e1ec87033d44d8d9e55b6a15a06e4412eb81a.tar.bz2 yosys-399e1ec87033d44d8d9e55b6a15a06e4412eb81a.zip | |
Cleanup
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 224a2d504..f6592098b 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -756,7 +756,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_assert(driving_lut); RTLIL::SigBit a_bit = not_cell->getPort("\\A"); RTLIL::SigBit y_bit = not_cell->getPort("\\Y"); - driving_lut = module->cell(remap_name(driving_lut->name)); log_assert(driving_lut); RTLIL::Const driver_lut = driving_lut->getParam("\\LUT"); for (auto &b : driver_lut.bits) { @@ -772,11 +771,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (sink_cell->type != "$lut") goto duplicate_lut; - //static int count = 0; - //log_warning("%d\n", count); - //if (count++ >= 41) - // goto duplicate_lut; - for (auto sink_cell : it->second) { SigSpec A = sink_cell->getPort("\\A"); RTLIL::Const mask = sink_cell->getParam("\\LUT"); @@ -805,7 +799,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri duplicate_lut: auto not_cell_name = not_cell->name; module->remove(not_cell); -#if 0 +#if 1 auto driver_a = driving_lut->getPort("\\A").chunks(); for (auto &chunk : driver_a) chunk.wire = module->wires_[remap_name(chunk.wire->name)]; |