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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 13:18:04 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 13:18:04 -0700 |
| commit | 0727b2c902df37fbbf2fe9acc31d96ce84fa88a7 (patch) | |
| tree | eac528db9ce7c933a9b3a083ada734543fe61a1b /passes | |
| parent | 8326af5418205e51452e0cced8d2253afe730e76 (diff) | |
| download | yosys-0727b2c902df37fbbf2fe9acc31d96ce84fa88a7.tar.gz yosys-0727b2c902df37fbbf2fe9acc31d96ce84fa88a7.tar.bz2 yosys-0727b2c902df37fbbf2fe9acc31d96ce84fa88a7.zip | |
Fix xilinx_dsp index cast
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 60e972615..51fd733d4 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -11,7 +11,7 @@ match ffA select ffA->type.in($dff, $dffe) select param(ffA, \CLK_POLARITY).as_bool() // select nusers(port(ffA, \Q)) == 2 - index <SigSpec> port(ffA, \Q).to_sigbit_pool() === port(dsp, \A).remove_const().to_sigbit_pool() + index <pool<SigBit>> port(ffA, \Q).to_sigbit_pool() === port(dsp, \A).remove_const().to_sigbit_pool() // DSP48E1 does not support clock inversion optional endmatch @@ -25,7 +25,7 @@ match ffB select ffB->type.in($dff, $dffe) select param(ffB, \CLK_POLARITY).as_bool() // select nusers(port(ffB, \Q)) == 2 - index <SigSpec> port(ffB, \Q).to_sigbit_pool() === port(dsp, \B).remove_const().to_sigbit_pool() + index <pool<SigBit>> port(ffB, \Q).to_sigbit_pool() === port(dsp, \B).remove_const().to_sigbit_pool() optional endmatch |