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* Walk through as many muxes as exist for rd_enEddie Hung2019-06-241-8/+16
* Merge pull request #1108 from YosysHQ/clifford/fix1091Eddie Hung2019-06-211-45/+99
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| * Replace "muxcover -freedecode" with "muxcover -dmux=cost"Clifford Wolf2019-06-211-15/+14
| * Add "muxcover -freedecode"Clifford Wolf2019-06-211-0/+14
| * Improvements in muxcoverClifford Wolf2019-06-201-38/+55
| * Add support for partial matches to muxcover, fixes #1091Clifford Wolf2019-06-201-7/+31
* | Merge pull request #1085 from YosysHQ/eddie/shregmap_improveEddie Hung2019-06-211-3/+15
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| * | Actually, there might not be any harm in updating sigmap...Eddie Hung2019-06-201-3/+1
| * | Add comment as per @cliffordwolfEddie Hung2019-06-201-0/+11
| * | Revert "Try way that doesn't involve creating a new wire"Eddie Hung2019-06-111-15/+10
| * | Try way that doesn't involve creating a new wireEddie Hung2019-06-111-10/+15
| * | If d_bit already in sigbit_chain_next, create extra wireEddie Hung2019-06-101-3/+6
* | | Merge pull request #1117 from bwidawsk/more-homeClifford Wolf2019-06-211-0/+4
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| * | Add a few more filename rewritesBen Widawsky2019-06-201-0/+4
* | | Fix typo, fixes #1095Clifford Wolf2019-06-201-1/+1
* | | Improve shregmap help message, fixes #1113Clifford Wolf2019-06-201-0/+2
* | | Fix typoClifford Wolf2019-06-201-2/+2
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* | Fixed the help summary line for a few commandsacw12512019-06-193-5/+5
* | Fix bug in #1078, add entry to CHANGELOGEddie Hung2019-06-191-3/+3
* | Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
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* Allow muxcover costs to be changedEddie Hung2019-06-071-12/+42
* Merge pull request #1071 from YosysHQ/eddie/fix_1070Clifford Wolf2019-06-061-2/+2
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| * Fix typo in opt_rmdffEddie Hung2019-06-051-2/+2
* | Merge pull request #1072 from YosysHQ/eddie/fix_1069Clifford Wolf2019-06-061-0/+5
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| * | Error out if no top module given before 'sim'Eddie Hung2019-06-051-0/+5
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* / Missing doc for -tech xilinx in shregmapEddie Hung2019-06-051-0/+3
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* Merge pull request #1067 from YosysHQ/clifford/fix1065Eddie Hung2019-06-051-1/+1
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| * Suppress driver-driver conflict warning for unknown cell types, fixes #1065Clifford Wolf2019-06-051-1/+1
* | Major rewrite of wire selection in setundef -initClifford Wolf2019-06-051-30/+89
* | Indent fixClifford Wolf2019-06-051-23/+25
* | Merge pull request #999 from jakobwenzel/setundefInitFixClifford Wolf2019-06-051-16/+23
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| * | initialize more registers in setundef -initJakob Wenzel2019-05-091-16/+23
* | | Fix typo in fmcombine log message, fixes #1063Clifford Wolf2019-06-051-2/+2
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* | Fix "tee" handling of log_streamsClifford Wolf2019-05-311-0/+5
* | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-4/+11
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| * | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-4/+11
* | | Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-102/+143
* | | Merge branch 'master' into wandworStefan Biereigel2019-05-272-6/+71
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| * | Merge pull request #1026 from YosysHQ/clifford/fix1023Clifford Wolf2019-05-271-2/+3
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| | * | Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023Clifford Wolf2019-05-221-2/+3
| * | | Revert enable checkEddie Hung2019-05-251-3/+1
| * | | opt_rmdff to optimise even in presence of enable signal, even removingEddie Hung2019-05-241-12/+29
| * | | Add commentsEddie Hung2019-05-241-1/+22
| * | | Resolve @cliffordwolf review, set even if !has_initEddie Hung2019-05-241-2/+1
| * | | Fix spacingEddie Hung2019-05-231-2/+2
| * | | opt_rmdff to work on $dffe and $_DFFE_*Eddie Hung2019-05-231-3/+32
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* / / move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-1/+77
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* | Add "wreduce -keepdc", fixes #1016Clifford Wolf2019-05-201-1/+9
* | Improvements in opt_cleanClifford Wolf2019-05-151-10/+10
* | Do not leak file descriptors in cover.ccClifford Wolf2019-05-151-5/+6