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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-25 12:55:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-25 12:55:57 -0700 |
| commit | d4fb6cac7c4c93f868e294dfc95936516813eeac (patch) | |
| tree | fa62016712cb927a36fa80bf7a416f9124df8964 /passes | |
| parent | f3e86e06e698491b110ac66b88bc3c0ce3cda174 (diff) | |
| download | yosys-d4fb6cac7c4c93f868e294dfc95936516813eeac.tar.gz yosys-d4fb6cac7c4c93f868e294dfc95936516813eeac.tar.bz2 yosys-d4fb6cac7c4c93f868e294dfc95936516813eeac.zip | |
Revert enable check
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index d10cf508f..2abffa2a9 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -385,9 +385,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) // (ii) reset value is same as constant D // and (a) has no initial value // (b) initial value same as constant D - // and (1) has no enable signal - // (2) enable is always active - if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const()) && (!sig_e.size() || (sig_d.is_fully_undef() && !has_init))) { + if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) { // Q is permanently D mod->connect(sig_q, sig_d); goto delete_dff; |