diff options
| author | Clifford Wolf <clifford@clifford.at> | 2019-05-22 13:56:56 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-22 13:57:36 +0200 |
| commit | e3f9ccf56d65ba72dfa625e9716d1182f36a381e (patch) | |
| tree | 294bb27b751b227ebc42f602767169eda2358b34 /passes | |
| parent | 0971f772d7975a3e6e3772838ce8e333a2a088c4 (diff) | |
| download | yosys-e3f9ccf56d65ba72dfa625e9716d1182f36a381e.tar.gz yosys-e3f9ccf56d65ba72dfa625e9716d1182f36a381e.tar.bz2 yosys-e3f9ccf56d65ba72dfa625e9716d1182f36a381e.zip | |
Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_clean.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index bf8020169..7011d4602 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -319,8 +319,9 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos wire->attributes.erase("\\init"); if (GetSize(wire) == 0) { - // delete zero-width wires - goto delete_this_wire; + // delete zero-width wires, unless they are module ports + if (wire->port_id == 0) + goto delete_this_wire; } else if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) { // do not delete anything with "keep" or module ports or initialized wires |